公开(公告)号：US06383825B1

公开(公告)日：2002-05-07

申请号：US09902396

申请日：2001-07-10

申请人： Warren M. Farnworth ,  Alan G. Wood

发明人： Warren M. Farnworth ,  Alan G. Wood

IPC分类号： H01L2166

CPC分类号： H01L22/22 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A method and system for making known good semiconductor dice are provided. The method includes providing a semiconductor die with programmable links, such as fuses or anti-fuses, that permit defects on the die to be corrected during a testing procedure. The system includes a testing apparatus in electrical communication with testing circuitry and with programming circuitry. During the testing procedure defects on the die can be detected and then corrected by selective actuation of the programmable links. Once the defects have been corrected the rehabilitated die can be retested and reburned-in, if necessary, for certification as a known good die. In an illustrative embodiment, the testing apparatus is adapted to electrically connect to multiple dice individually packaged in temporary packages. In an alternate embodiment, the testing apparatus comprises a board adapted to electrically connect to multiple unpackaged dice. In another alternate embodiment the testing apparatus comprises a board adapted to electrically connect to a semiconductor wafer comprising a plurality of dice.

摘要翻译： 提供了制造已知的良好半导体晶片的方法和系统。 该方法包括提供具有诸如保险丝或抗熔丝等可编程链路的半导体管芯，其允许在测试过程期间校正管芯上的缺陷。 该系统包括与测试电路和编程电路进行电气通信的测试装置。 在测试过程中，可以检测模具上的缺陷，然后通过可编程链路的选择性启动来校正缺陷。 一旦缺陷得到纠正，修复后的模具就可以重新测试，如果需要，可以重新进行认证，作为一个已知的好死者。 在说明性实施例中，测试装置适于电连接到单独封装在临时包装中的多个骰子。 在替代实施例中，测试装置包括适于电连接到多个未封装的裸片的板。 在另一替代实施例中，测试装置包括适于电连接到包括多个裸片的半导体晶片的板。

公开(公告)号：US06319354B1

公开(公告)日：2001-11-20

申请号：US09693443

申请日：2000-10-20

申请人： Warren M. Farnworth ,  Alan G. Wood

发明人： Warren M. Farnworth ,  Alan G. Wood

IPC分类号： B32B3500

CPC分类号： H01L21/6835 ,  B28D5/0094 ,  H01L21/3043 ,  H01L21/481 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68313 ,  H01L2221/68327 ,  H01L2224/4824 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10S156/941 ,  Y10S438/976 ,  Y10T156/11 ,  Y10T156/1132 ,  Y10T156/19 ,  Y10T156/1944 ,  H01L2924/00

摘要： A method and system for dicing semiconductor components, such as bare dice and chip scale packages, are provided. Initially, the semiconductor components are contained on a wafer or a panel. Next, an insert that includes a base and an adhesive layer, is used to support the substrate for separation into separate components by sawing or other process. The insert with the separated components retained thereon, is then transferred to a carrier tray constructed according to JEDEC standards. The carrier tray is adapted for stacking and for handling by conveyors, magazines and other standard equipment. The system includes the substrate, the insert, and the standardized carrier tray.

摘要翻译： 提供了用于切割半导体部件的方法和系统，例如裸裸片和芯片级封装。 最初，半导体元件被包含在晶片或面板上。 接下来，包括基底和粘合剂层的插入物用于通过锯切或其它工艺来支撑基底以分离成单独的部件。 然后将保留在其上的分离的部件的插入物转移到根据JEDEC标准构造的载体托盘。 托盘适于堆放和由输送机，杂志和其他标准设备进行处理。 该系统包括基板，插入件和标准化托盘。

公开(公告)号：US06296171B1

公开(公告)日：2001-10-02

申请号：US09416248

申请日：1999-10-12

申请人： David R. Hembree ,  Michael E. Hess ,  John O. Jacobson ,  Warren M. Farnworth ,  Alan G. Wood

发明人： David R. Hembree ,  Michael E. Hess ,  John O. Jacobson ,  Warren M. Farnworth ,  Alan G. Wood

IPC分类号： B23K106

CPC分类号： B23K20/10 ,  B23K2101/38

摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.

摘要翻译： 用于将互连的穿刺型导电接触构件接合到裸半导体管芯的接合焊盘的机器和方法包括使用安装成振动模具和互连中的一个或两者的一个或两个超声波振动器。 超声能量的短轴向线性爆发使得接触构件能够以低得多的压缩力在接合焊盘的表面上刺穿硬氧化物层并且迅速地实现完全的穿透深度。

公开(公告)号：US06258609B1

公开(公告)日：2001-07-10

申请号：US08719850

申请日：1996-09-30

申请人： Warren M. Farnworth ,  Alan G. Wood

发明人： Warren M. Farnworth ,  Alan G. Wood

IPC分类号： H01L2166

CPC分类号： H01L22/22 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A method and system for making known good semiconductor dice are provided. The method includes providing a semiconductor die with programmable links, such as fuses or anti-fuses, that permit defects on the die to be corrected during a testing procedure. The system includes a testing apparatus in electrical communication with testing circuitry and with programming circuitry. During the testing procedure defects on the die can be detected and then corrected by selective actuation of the programmable links. Once the defects have been corrected the rehabilitated die can be retested and reburned-in, if necessary, for certification as a known good die. In an illustrative embodiment, the testing apparatus is adapted to electrically connect to multiple dice individually packaged in temporary packages. In an alternate embodiment, the testing apparatus comprises a board adapted to electrically connect to multiple unpackaged dice. In another alternate embodiment the testing apparatus comprises a board adapted to electrically connect to a semiconductor wafer comprising a plurality of dice.

摘要翻译： 提供了制造已知的良好半导体晶片的方法和系统。 该方法包括提供具有诸如保险丝或抗熔丝等可编程链路的半导体管芯，其允许在测试过程期间校正管芯上的缺陷。 该系统包括与测试电路和编程电路进行电气通信的测试装置。 在测试过程中，可以检测模具上的缺陷，然后通过可编程链路的选择性启动来校正缺陷。 一旦缺陷得到纠正，修复后的模具就可以重新测试，如果需要，可以重新进行认证，作为一个已知的好死者。 在说明性实施例中，测试装置适于电连接到单独封装在临时包装中的多个骰子。 在替代实施例中，测试装置包括适于电连接到多个未封装的裸片的板。 在另一替代实施例中，测试装置包括适于电连接到包括多个裸片的半导体晶片的板。

公开(公告)号：US06208157B1

公开(公告)日：2001-03-27

申请号：US09298769

申请日：1999-04-23

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  G01R1/0433 ,  G01R1/0483

摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

公开(公告)号：US6150717A

公开(公告)日：2000-11-21

申请号：US98197

申请日：1998-06-16

申请人： Alan G. Wood ,  Warren M. Farnworth ,  Ford Grigg ,  Salman Akram

发明人： Alan G. Wood ,  Warren M. Farnworth ,  Ford Grigg ,  Salman Akram

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/10165 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A semiconductor package and method for fabricating the package are provided. The package includes a housing having individual channels, each adapted to retain a semiconductor die in electrical communication with electrical connectors. The dice can include solder bumps, formed on electrodes, using electroless deposition and wave soldering. For fabricating the package, the dice can be inserted into the channels, with the electrical connectors on the housing proximate to the solder bumps on the dice. The solder bumps can then be reflowed to form bonded connections with the electrical connectors. In an alternate embodiment, conductive adhesive bumps, rather than solder bumps, are formed on the dice to provide compliant connections with the electrical connectors on the housing. In addition, the conductive adhesive bumps can be cured while in contact with the electrical connectors to form bonded connections. Other alternate embodiments include a chip scale package, a temporary package for testing bare dice, and a multi chip module.

摘要翻译： 提供一种用于制造封装的半导体封装和方法。 封装包括具有单独通道的壳体，每个通道适于保持与电连接器电连通的半导体管芯。 骰子可以包括使用无电沉积和波峰焊在电极上形成的焊料凸块。 为了制造封装，可以将骰子插入通道中，外壳上的电连接器靠近骰子上的焊料凸块。 然后可以将焊料凸起回流以与电连接器形成粘合连接。 在替代实施例中，导电粘合剂凸块而不是焊料凸块形成在芯片上，以提供与壳体上的电连接器的柔性连接。 此外，导电粘合剂凸块可以在与电连接器接触的同时固化，以形成接合连接。 其他替代实施例包括芯片级封装，用于测试裸裸片的临时封装以及多芯片模块。

公开(公告)号：US6114240A

公开(公告)日：2000-09-05

申请号：US250289

申请日：1999-02-12

申请人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood

发明人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H01L21/44

CPC分类号： H05K1/112 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/16237 ,  H01L2224/82039 ,  H01L2225/1005 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0306 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K3/0029 ,  H05K3/0032

摘要： A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts on the component, using a laser beam that is focused to produce a desired via geometry. The vias can include enlarged end portions to facilitate deposition of a conductive material during formation of the vias, and to provide an increased surface area for forming the contacts. For example, by focusing the laser beam at a midpoint of a substrate of the component, an hour glass via geometry is provided. Alternately, the laser beam can be focused at an exit point, or at an entry point of the substrate, to provide converging or diverging via geometries. The method can also include forming contact pins on the conductive vias by bonding and shaping metal wires using a wire bonding process, or a welding process.

摘要翻译： 提供了一种制造诸如封装，互连和测试载体的半导体部件的方法。 该方法包括激光加工用于使部件上的触点互连的导电通孔，使用聚焦以产生所需通孔几何形状的激光束。 通孔可以包括扩大的端部，以便于在形成通孔期间沉积导电材料，并且提供用于形成触点的增加的表面积。 例如，通过将激光束聚焦在部件的基板的中点处，提供了小时玻璃通孔几何形状。 或者，激光束可以在出口点处或在基板的入口处聚焦，以提供会聚或发散的几何形状。 该方法还可以包括通过使用引线接合工艺或焊接工艺接合和成形金属线来在导电通孔上形成接触引脚。

公开(公告)号：US6091252A

公开(公告)日：2000-07-18

申请号：US312381

申请日：1999-05-14

申请人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  G01R1/06 ,  G01R31/26

CPC分类号： G01R1/0466

摘要： A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

摘要翻译： 提供了一种用于与具有接触凸块的半导体部件建立临时电连通的方法，装置和系统。 该装置包括具有适于电接触接触凸点的接触构件图案的互连。 每个接触构件包括与相关导体电连通的一个或多个导电突起的阵列。 突起形成接触构件，用于保持半导体部件上的各个接触凸块。 突起可以是具有覆盖有导电层的成角度表面的柱。 替代地，突起可以是沉积在基底上的材料，或者可以是在结合到基底的多层带上形成的微胶囊。 互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者在用于测试裸露骰子或凸起的芯片级封装的芯片级测试系统中。

公开(公告)号：US6060891A

公开(公告)日：2000-05-09

申请号：US797719

申请日：1997-02-11

申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

IPC分类号： G01R1/073 ,  G01R31/28

CPC分类号： G01R1/073 ,  G01R31/2886

摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

公开(公告)号：US6020624A

公开(公告)日：2000-02-01

申请号：US53273

申请日：1998-04-01

申请人： Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

发明人： Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H01L29/06 ,  H01L23/02 ,  H01L23/28

CPC分类号： H05K3/4007 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/85 ,  G01R1/06738 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73207 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

摘要： A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.

摘要翻译： 提供一种用于形成用于半导体器件的互连的方法。 互连包括被导电层覆盖的凸起的接触结构，并且具有用于穿透用于半导体器件的触点的穿透突起。 在说明性实施例中，互连可用于形成双衬底裸片。 用于双衬底裸片的互连衬底包括控制和逻辑电路，并且用于双衬底裸片的存储器衬底包括存储器阵列。 互连还可用于建立与常规裸片上形成的微观触点的电连接。 此外，互连可以由用于接触微观触点的三维微结构形成。 此外，互连可以形成为用于电接触包含在晶片上的骰子或用于堆叠多个晶片的晶片互连。