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    Wiring board and method of manufacturing the same
    83.
    发明授权
    Wiring board and method of manufacturing the same 有权
    接线板及其制造方法

    公开(公告)号：US08785786B2

    公开(公告)日：2014-07-22

    申请号：US13325767

    申请日：2011-12-14

    Applicant: Erina Yamada ,  Kazunaga Higo ,  Hironori Sato

    Inventor： Erina Yamada ,  Kazunaga Higo ,  Hironori Sato

    IPC: H05K1/09 ,  B23K1/00

    CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H05K3/244 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2203/054

    Abstract: A wiring board including a conductor post corresponding to high-density packaging is provided. The wiring board may comprise a conductor layer, a solder resist layer laminated on the conductor layer, and a conductor post that is electrically connected to a conductor layer which is disposed in a lower portion of a through-hole provided in the solder resist layer, wherein the solder resist layer comprises a thermosetting resin; the conductor post comprises tin, copper, or a solder; the conductor post includes a lower conductor post, which is located within the through-hole and includes an external side surface and a lower end surface, and an upper conductor post, which is located above the lower conductor post and is projected outside the solder resist layer; and at least a part of a lower end surface of the upper conductor post is brought into intimate contact with an outer surface of the solder resist layer.

    Abstract translation: 提供了包括对应于高密度封装的导体柱的布线板。 布线基板可以包括导体层，层叠在导体层上的阻焊层，以及导体柱，其电连接到布置在设置在阻焊层中的通孔的下部的导体层， 其中所述阻焊层包含热固性树脂; 导体柱包括锡，铜或焊料; 导体柱包括位于通孔内并包括外侧表面和下端表面的下导体柱和位于下导体柱上方并被突出在阻焊层外侧的上导体柱 层; 并且上导体柱的下端表面的至少一部分与阻焊层的外表面紧密接触。

    Underbump metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack
    85.
    发明授权
    Underbump metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack 有权
    使用电解Cu /电解Ni /电解铜叠层的底部衬底冶金

    公开(公告)号：US08587112B2

    公开(公告)日：2013-11-19

    申请号：US13453074

    申请日：2012-04-23

    Applicant: Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

    Inventor： Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

    IPC: H05K3/00

    CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/24 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0769 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

    Abstract: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

    Abstract translation: 在包含芯，至少一个前金属互连层和至少一个背侧金属互连层的封装基板的每一侧上形成化学镀铜层。 在两个无电镀铜层上涂布光致抗蚀剂，并用光刻图案化。 第一电解Cu部分形成在无电解Cu层的暴露表面上，随后形成电解Ni部分和第二电解Cu部分。 电解Ni部分提供增强的电迁移阻力，而第二电解Cu部分提供用于焊接掩模的粘附层并且用作氧化保护层。 一些第一电解铜可以被光刻装置掩盖，以根据需要阻挡电解Ni部分和第二电解Cu部分的形成。 任选地，电解Ni部分可以直接形成在无电镀Cu层上。

    SURFACE TREATMENT STRUCTURE OF CIRCUIT PATTERN
    86.
    发明申请
    SURFACE TREATMENT STRUCTURE OF CIRCUIT PATTERN 审中-公开
    电路图形表面处理结构

    公开(公告)号：US20130233602A1

    公开(公告)日：2013-09-12

    申请号：US13416158

    申请日：2012-03-09

    Applicant: Ting-Hao Lin ,  Yu-Hui Wu

    Inventor： Ting-Hao Lin ,  Yu-Hui Wu

    IPC: H05K1/09

    CPC classification number: H05K3/243 ,  H01L2224/13111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/81444 ,  H01L2224/85444 ,  H05K3/24 ,  H05K2201/0341 ,  H01L2924/00014

    Abstract: A surface treatment structure formed on a circuit pattern on a printed circuit board is provided, which includes a first gold layer, a palladium layer, and a second gold layer stacked from bottom to top, respectively, or includes a palladium layer, and a second gold layer stacked from bottom to top, respectively. The palladium layer is used to prevent the diffusion of the copper ions from the circuit pattern. Only a thin surface treatment structure of the circuit pattern of the present invention is required to achieve excellent wire bonding, so that the overall thickness is reduced, and the manufacture cost is also reduced. Furthermore, the uniformness of palladium is better than that of nickel, and thereby the surface treatment structure of the circuit pattern of the present invention is suitably used for manufacturing the fine-line circuits, thereby having a wider industrial applicability.

    Abstract translation: 提供了形成在印刷电路板上的电路图案上的表面处理结构，其包括分别从底部至顶部堆叠的第一金层，钯层和第二金层，或包括钯层，第二金层 金层分别从底部到顶部堆叠。 钯层用于防止铜离子从电路图案扩散。 需要本发明的电路图形的薄的表面处理结构来实现优良的引线接合，从而减小总体厚度，并且制造成本也降低。 此外，钯的均匀性优于镍，因此本发明的电路图案的表面处理结构适用于制造细线电路，从而具有更广的工业实用性。

    Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack
    87.
    发明授权
    Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack 失效
    使用电解Cu /电解Ni /电解铜叠层的凸坑冶金

    公开(公告)号：US08232655B2

    公开(公告)日：2012-07-31

    申请号：US11968663

    申请日：2008-01-03

    Applicant: Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

    Inventor： Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

    IPC: H01L23/495 ,  H01L21/44

    CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/24 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0769 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

    Abstract: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

    Abstract translation: 在包含芯，至少一个前金属互连层和至少一个背侧金属互连层的封装基板的每一侧上形成化学镀铜层。 在两个无电镀铜层上涂布光致抗蚀剂，并用光刻图案化。 第一电解Cu部分形成在无电解Cu层的暴露表面上，随后形成电解Ni部分和第二电解Cu部分。 电解Ni部分提供增强的电迁移阻力，而第二电解Cu部分提供用于焊接掩模的粘附层并且用作氧化保护层。 一些第一电解铜可以被光刻装置掩盖，以根据需要阻挡电解Ni部分和第二电解Cu部分的形成。 任选地，电解Ni部分可以直接形成在无电镀Cu层上。

    WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF
    88.
    发明申请
    WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    接线基板及其制造方法

    公开(公告)号：US20110297426A1

    公开(公告)日：2011-12-08

    申请号：US13153590

    申请日：2011-06-06

    Applicant: Masahiro SUNOHARA ,  Shigeaki SUGANUMA

    Inventor： Masahiro SUNOHARA ,  Shigeaki SUGANUMA

    IPC: H05K1/09 ,  H05K3/20

    CPC classification number: H01L23/49822 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/388 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/10378 ,  H01L2924/00

    Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked with a copper alloy layer formed adjacent to the adhesive layer and interposed between the electrode layer and the wiring layer.

    Abstract translation: 布线基板包括由铜制成的布线层，由铜制成的电极层和与电极层相邻布置的绝缘层。 布线层堆叠在电极层和绝缘层上。 绝缘层和布线层被叠置在介于绝缘层和布线层之间的粘合剂层。 电极层和布线层与形成在粘合剂层附近的铜合金层层叠，插入在电极层和布线层之间。

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