公开(公告)号：US08433839B2

公开(公告)日：2013-04-30

申请号：US13274344

申请日：2011-10-16

Applicant: Zheng-Heng Sun

Inventor： Zheng-Heng Sun

IPC: H05K7/10

CPC classification number: H05K1/029 ,  H05K1/141 ,  H05K2201/09954 ,  H05K2201/10045 ,  H05K2201/10189

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract translation: 连接器组件包括第一至第五连接器，两个PCIe插槽和适配器板。 当第一连接器连接到第五连接器，并且第三连接器连接到第四连接器时，第三连接器的引脚处的信号通过第四连接器传送到第一PCIe插槽的第二组引脚，第五连接器 连接器和串联的第一连接器。 当第二连接器连接到第五连接器，并且第三连接器连接到第四连接器时，通过第四连接器将第三连接器的引脚处的信号传输到第二PCIe插槽的第四组引脚，第五连接器 ，第二连接器串联。

公开(公告)号：US20130042040A1

公开(公告)日：2013-02-14

申请号：US13274344

申请日：2011-10-16

Applicant: ZHENG-HENG SUN

Inventor： ZHENG-HENG SUN

IPC: G06F13/00

CPC classification number: H05K1/029 ,  H05K1/141 ,  H05K2201/09954 ,  H05K2201/10045 ,  H05K2201/10189

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract translation: 连接器组件包括第一至第五连接器，两个PCIe插槽和适配器板。 当第一连接器连接到第五连接器，并且第三连接器连接到第四连接器时，第三连接器的引脚处的信号通过第四连接器传送到第一PCIe插槽的第二组引脚，第五连接器 连接器和串联的第一连接器。 当第二连接器连接到第五连接器，并且第三连接器连接到第四连接器时，通过第四连接器将第三连接器的引脚处的信号传输到第二PCIe插槽的第四组引脚，第五连接器 ，第二连接器串联。

公开(公告)号：US20120147567A1

公开(公告)日：2012-06-14

申请号：US12964503

申请日：2010-12-09

Applicant: Yun-Han Lee ,  Mark Shane Peng ,  Shyh-An Chi

Inventor： Yun-Han Lee ,  Mark Shane Peng ,  Shyh-An Chi

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H01L23/147 ,  H01L23/538 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K2201/10045 ,  H05K2201/10053 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.

Abstract translation: 一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。 内插器基本上没有内置的功能元件。 功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。

公开(公告)号：US20080303149A1

公开(公告)日：2008-12-11

申请号：US10593535

申请日：2005-01-21

Applicant: Toshiharu Takayama ,  Ryuusuke Suzuki ,  Takefumi Nakamori

Inventor： Toshiharu Takayama ,  Ryuusuke Suzuki ,  Takefumi Nakamori

IPC: H01L23/488

CPC classification number: H01C1/16 ,  H01C1/144 ,  H01C13/02 ,  H01G4/40 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10045 ,  H05K2201/10234 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic component including, on one surface of a substrate (1), a plurality of circuit elements and external terminals each consisting of a conductive protrusion (9) for the circuit elements is provided with a structure capable of resisting an external force after mounting. Each of the circuit elements includes, as constituent elements, a pair of electrodes (2) and a resistive element (3) or a dielectric contacting with the pair of electrodes (2), each circuit element is covered with an overcoat (7) while the electrodes (2) are partially exposed as lands (4), the conductive protrusion (9) includes a fixedly bonding member, the conductive protrusion (9) is fixedly bonded to each of the lands (4) by the fixedly bonding member, at least three lands (4b) of the lands (4) are larger in area than the other lands (4a), the electronic component can stand alone while the conductive protrusion (9) contacts with a flat if the conductive protrusion (9) is fixedly bonded only to each of the larger-area lands (4b), and the conductive protrusions are all formed by fixedly bonding conductive balls (10) substantially equal in size to entire surfaces of the respective lands (4).

Abstract translation: 一种电子部件，在基板（1）的一个表面上具有由电路元件用的导电突起（9）构成的多个电路元件和外部端子，其具有能够抵抗安装后的外力的结构。 每个电路元件包括作为组成元件的一对电极（2）和电阻元件（3）或与该对电极（2）接触的电介质，每个电路元件被外涂层（7）覆盖，同时 电极（2）部分地露出为焊盘（4），导电突起（9）包括固定接合部件，导电突起（9）通过固定接合部件固定地接合到每个焊盘（4）上， 如果导电突起（9）固定地，导电突起（9）与平坦接触，则电子部件可以独立地平坦地区域（4）中的至少三个焊盘区域（4b）的面积大于其他焊盘（4a） 仅与每个较大区域焊盘（4b）接合，并且导电突起全部通过将导电球（10）固定地结合到大致相等于各个焊盘（4）的整个表面上而形成。

公开(公告)号：US07217043B2

公开(公告)日：2007-05-15

申请号：US11133782

申请日：2005-05-20

Applicant: Nikolaus Schunk

Inventor： Nikolaus Schunk

IPC: G02B6/43 ,  H04B10/00

CPC classification number: G02B6/305 ,  G02B6/02033 ,  G02B6/3885 ,  G02B6/421 ,  G02B6/4246 ,  H05K1/0203 ,  H05K1/147 ,  H05K2201/10045 ,  H05K2201/10121 ,  H05K2201/1056

Abstract: An opto-electronic transceiver having: a transmitting component for converting electrical signals into optical signals; a first circuitry module for the transmitting component; a receiving component for converting optical signals into electrical signals; a second circuitry module for the receiving component; a printed circuitboard with conductor tracks, on which the transmitting component, the receiving component, the first circuitry module and the second circuitry module are arranged; and a transceiver housing including a nonconductive material and has a connector receptacle for receiving and coupling an optical connector. The transmitting component, the first circuitry module, the receiving component and the second circuitry module form at least one subassembly, the subassembly having: an encapsulation composition, in which the components of the subassembly are embedded, and a wiring layer embodied using thin-film technology, the wiring layer providing an electrical contact connection between the subassembly components and to associated contacts of the printed circuit board.

Abstract translation: 一种光电收发器，具有：用于将电信号转换为光信号的发送部件; 用于所述发射部件的第一电路模块; 用于将光信号转换成电信号的接收部件; 用于所述接收部件的第二电路模块; 具有导体轨迹的印刷电路板，其上布置有发射部件，接收部件，第一电路模块和第二电路模块; 以及收发器壳体，其包括非导电材料并且具有用于接收和耦合光学连接器的连接器插座。 发射部件，第一电路模块，接收部件和第二电路模块形成至少一个子组件，该子组件具有：嵌入组件的部件的封装组合物，以及使用薄膜实现的布线层 技术，布线层提供子组件部件之间的电接触连接和印刷电路板的相关联的接触。

公开(公告)号：US20070096864A1

公开(公告)日：2007-05-03

申请号：US10579680

申请日：2004-11-12

Applicant: Koji Fujimoto

Inventor： Koji Fujimoto

IPC: H01C1/012

CPC classification number: H05K3/3442 ,  H01C1/16 ,  H01C13/02 ,  H01C17/006 ,  H01C17/28 ,  H05K2201/10045 ,  Y02P70/613

Abstract: The present invention provides a surface mount composite electronic component which can be made compact. The structure of the surface mount composite electronic component is one in which a circuit element is formed on each of a set of opposing surfaces of an insulating substrate composed of a hexahedron, with electrodes that make up the circuit elements also functioning as external terminals. For example, a pair of first electrodes disposed on both ends of a front surface of the insulating substrate composed of a hexahedron, a pair of second electrodes disposed on a rear surface of the insulating substrate opposite the first electrodes, a first resistor disposed so as to contact both of the first pair of electrodes, and a second resistor disposed so as to contact both of the second electrodes.

Abstract translation: 本发明提供一种可以制成紧凑的表面安装复合电子部件。 表面安装复合电子部件的结构是其中在由六面体组成的绝缘基板的一组相对表面的每一个上形成电路元件的结构，其中构成电路元件的电极也用作外部端子。 例如，设置在由六面体构成的绝缘基板的前表面的两端上的一对第一电极，设置在与第一电极相对的绝缘基板的后表面上的一对第二电极，第一电阻器设置为 以接触第一对电极中的两个，以及设置成接触两个第二电极的第二电阻器。

公开(公告)号：US20070064375A1

公开(公告)日：2007-03-22

申请号：US11513039

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

IPC: H01G4/06

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A circuit board (10, 10″, 10″′) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101″′, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101″′, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

Abstract translation: 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后部电容器（102）的陶瓷电容器（101,101'，101“，101”'，101“'，101”'，101“'，101”'，101“ 电容器表面（103），其具有第一内部电极层（141）和第二内部电极层（142）与陶瓷介电层（105）交替层叠的结构，并且具有多个电容器功能单元 （101,101'，101“，101”，101“，101”，101“，101”，101“，101”，101“ ）以主芯表面（12）和主电容器表面（102）指向相同方向的状态埋在板芯（11）中; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

公开(公告)号：US20030075356A1

公开(公告)日：2003-04-24

申请号：US10257205

申请日：2002-10-09

Inventor： Kenichi Horie

IPC: H05K001/03

CPC classification number: H05K1/186 ,  H01L23/66 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/183 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/10045 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: It is an object of the invention to provide an electronic device in which a passive element with an excellent element characteristic is embedded and a method of manufacturing the same. It is another object of the invention to provide an electronic device which makes miniaturization thereof possible and a method of manufacturing the same. A body (10) and a functional block (30) are stuck together by accommodating the functional block (30) in an opening of green ceramic sheets and then sintering those sheets. A temperature for sintering sheets to constitute a dielectric portion (31) of the functional block (30) can be different from that for sintering a raw material of a ceramic material to constitute a dielectric portion (12) of the body (10). Flexibility in selecting a material of the dielectric portion (31) can be extended and a material with a low dielectric constant can be selected for the dielectric portion (31). A dielectric constant of the ceramic material of the functional block (30) can be higher to realize miniaturization of the functional block (30). Since conductor patterns of the functional block (30) can be formed by means of thin film technologies, a three-dimensional appearance is given to edges of the conductor patterns, thereby the functional block (30) with a high Q-value can be embedded in the body (10).

Abstract translation: 本发明的一个目的是提供一种其中嵌有具有优异元件特性的无源元件的电子器件及其制造方法。 本发明的另一个目的是提供使其小型化成为可能的电子设备及其制造方法。 将主体（10）和功能块（30）通过将功能块（30）容纳在生坯陶瓷片的开口中而粘合在一起，然后烧结这些片。 构成功能块（30）的电介质部（31）的烧结片的温度可以不同于用于烧结构成本体（10）的电介质部（12）的陶瓷材料的原料的温度。 可以延长选择电介质部分（31）的材料的灵活性，并且可以为电介质部分（31）选择具有低介电常数的材料。 功能块（30）的陶瓷材料的介电常数可以更高以实现功能块（30）的小型化。 由于可以通过薄膜技术形成功能块（30）的导体图案，因此可以对导体图案的边缘进行三维外观，从而可以嵌入具有高Q值的功能块（30） 在身体（10）。

公开(公告)号：US06440318B1

公开(公告)日：2002-08-27

申请号：US09507579

申请日：2000-02-18

Applicant: Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

Inventor： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC: H01B1300

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

Abstract translation: 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US20020015293A1

公开(公告)日：2002-02-07

申请号：US09956909

申请日：2001-09-21

Inventor： Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

IPC: H05K001/16 ,  H05K001/11

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.

Abstract translation: 通过将电源层的电位波动相对于在切换IC器件等而发生的接地层的电位波动转换为基底中的焦耳热而不使用任何部件作为对策来实现高安装密度的低EMI电路 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。 本发明通过吸收电源回路中发生的电位波动（谐振）可以显着地抑制不期望的辐射，通过等效地降低杂散电容的Q值，吸收平行板线匹配终止的驻波，闭合屏蔽 平行板线。