公开(公告)号：US20110127669A1

公开(公告)日：2011-06-02

申请号：US12935864

申请日：2009-03-18

Applicant: Hideki Mizuhara ,  Hajime Kobayashi ,  Toshiya Shimizu

Inventor： Hideki Mizuhara ,  Hajime Kobayashi ,  Toshiya Shimizu

IPC: H01L23/498 ,  H01L23/48 ,  H01B5/02 ,  B23K1/20

CPC classification number: B23K1/0016 ,  B23K31/02 ,  B23K35/262 ,  B23K35/3013 ,  B23K2101/42 ,  B32B15/018 ,  C22C13/00 ,  C22C13/02 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3463 ,  H05K2203/0435 ,  H01L2924/00

Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 μm.

Abstract translation: 本发明提供一种不太可能开发Sn晶须的焊料结构和形成这种焊料结构的方法。 焊料结构包括能够具有固液共存状态的Sn合金和覆盖Sn合金表面的至少一部分的Au（或Au合金）涂层。 Au覆盖层是覆盖并涂覆Sn合金表面的至少一部分的膜。 作为优选的方式，Au涂层在Sn合金的表面上形成网状结构。 Au涂层的厚度例如为1〜5μm。

公开(公告)号：US08344522B2

公开(公告)日：2013-01-01

申请号：US12935864

申请日：2009-03-18

Applicant: Hideki Mizuhara ,  Hajime Kobayashi ,  Toshiya Shimizu

Inventor： Hideki Mizuhara ,  Hajime Kobayashi ,  Toshiya Shimizu

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: B23K1/0016 ,  B23K31/02 ,  B23K35/262 ,  B23K35/3013 ,  B23K2101/42 ,  B32B15/018 ,  C22C13/00 ,  C22C13/02 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3463 ,  H05K2203/0435 ,  H01L2924/00

Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 μm.

Abstract translation: 本发明提供一种不太可能开发Sn晶须的焊料结构和形成这种焊料结构的方法。 焊料结构包括能够具有固液共存状态的Sn合金和覆盖Sn合金表面的至少一部分的Au（或Au合金）涂层。 Au覆盖层是覆盖并涂覆Sn合金表面的至少一部分的膜。 作为优选的方式，Au涂层在Sn合金的表面上形成网状结构。 Au涂层的厚度例如为1〜5μm。

公开(公告)号：US08183090B2

公开(公告)日：2012-05-22

申请号：US12856168

申请日：2010-08-13

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H05K3/10

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部上的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US08093699B2

公开(公告)日：2012-01-10

申请号：US11313743

申请日：2005-12-22

Applicant: Yasuhiro Kohara ,  Ryosuke Usui ,  Hideki Mizuhara ,  Yasunori Inoue

Inventor： Yasuhiro Kohara ,  Ryosuke Usui ,  Hideki Mizuhara ,  Yasunori Inoue

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/73203 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A circuit device in which highly reliable sealing with a resin can be achieved is provided. A semiconductor chip is provided on one surface of an insulating resin film and a conductive layer that is electrically connected to the semiconductor chip is provided on another surface of the insulating resin film. A solder ball (electrode) for the connection to a circuit board is provided on the conductive layer. An insulating resin layer is further provided between the conductive layer and the circuit board to embed the electrode therein. In this manner, the circuit device is formed. A side face of the semiconductor chip is covered with the insulating resin film.

Abstract translation: 提供了可以实现用树脂高度可靠的密封的电路装置。 在绝缘树脂膜的一个表面上设置半导体芯片，并且在绝缘树脂膜的另一个表面上设置与半导体芯片电连接的导电层。 用于连接电路板的焊球（电极）设置在导电层上。 在导电层和电路板之间还设置有绝缘树脂层，以将电极嵌入其中。 以这种方式形成电路装置。 半导体芯片的侧面被绝缘树脂膜覆盖。

公开(公告)号：US07855452B2

公开(公告)日：2010-12-21

申请号：US12022865

申请日：2008-01-30

Applicant: Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

Inventor： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area.The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract translation: 在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。 为了确保电极之间的大间隙，在电极上形成绝缘层。 还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。 重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。 绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。 重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。

公开(公告)号：US07553164B2

公开(公告)日：2009-06-30

申请号：US11416083

申请日：2006-05-01

Applicant: Ryosuke Usui ,  Hideki Mizuhara ,  Yasunori Inoue

Inventor： Ryosuke Usui ,  Hideki Mizuhara ,  Yasunori Inoue

IPC: H05K1/14

CPC classification number: H01L21/6835 ,  G01C19/56 ,  G01P1/023 ,  G01P15/18 ,  H01L21/4832 ,  H01L21/4842 ,  H01L21/568 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A circuit device of the present invention includes a first element which is placed parallel to a first reference plane and which senses a physical quantity, and a second element placed parallel to a second reference plane which intersects the first reference plane at a predetermined angle. The circuit device further includes a sealing resin for integrally sealing the first and second elements, a first conductive pattern which is electrically connected to the first element and placed parallel to the first reference plane and which has a back surface exposed from the sealing resin, and a second conductive pattern which is electrically connected to the second element and placed parallel to the second reference plane and which has a back surface exposed from the sealing resin.

Abstract translation: 本发明的电路装置包括平行于第一参考平面并感测物理量的第一元件和平行于与第一参考平面以预定角度相交的第二参考平面放置的第二元件。 电路装置还包括用于一体地密封第一和第二元件的密封树脂，与第一元件电连接并平行于第一参考平面放置并且具有从密封树脂露出的后表面的第一导电图案，以及 第二导电图案，其电连接到第二元件并且平行于第二参考平面放置，并且具有从密封树脂暴露的后表面。

公开(公告)号：US20090149034A1

公开(公告)日：2009-06-11

申请号：US12335150

申请日：2008-12-15

Applicant: Ryosuke USUI ,  Hideki Mizuhara ,  Takeshi Nakamura

Inventor： Ryosuke USUI ,  Hideki Mizuhara ,  Takeshi Nakamura

IPC: H01L21/26

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/28 ,  H05K3/284 ,  H05K3/381 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225

Abstract: In a semiconductor module, adhesion between an insulating base material and an insulator provided on the insulating base material, for example a sealing resin of the semiconductor element, is to be improved.A plurality of interconnect layers, each including an interlayer dielectric film 405 and a copper interconnect 407, is stacked and a solder resist layer 408 is formed on an uppermost layer. Elements 410a and 410b are formed on a surface of the solder resist layer 408. The elements 410a and 410b are molded in a molding resin 415. The surface of the solder resist layer 408 is modified by plasma processing under a specific condition so that minute projections are formed thereon. Such surface of the solder resist layer 408 is processed such that a value of y/x becomes not less than 0.4, where x represents a detected intensity at a binding energy of 284.5 eV and y represents a detected intensity at a binding energy of 286 eV, by an X-ray photoelectric spectroscopy spectrum.

Abstract translation: 在半导体模块中，将提高绝缘基材和设置在绝缘基材上的绝缘体（例如半导体元件的密封树脂）之间的粘附性。 层叠多个互连层，每个互连层包括层间绝缘膜405和铜互连407，并且在最上层形成阻焊层408。 元件410a和410b形成在阻焊层408的表面上。元件410a和410b被模制在模制树脂415中。阻焊层408的表面通过在特定条件下的等离子体处理而被修改，使得微小突起 形成在其上。 处理阻焊层408的这种表面使得y / x的值变为不小于0.4，其中x表示在284.5eV的结合能处的检测强度，y表示在结合能为286eV时的检测强度 ，通过X射线光电谱光谱。

公开(公告)号：US20080272502A1

公开(公告)日：2008-11-06

申请号：US12109811

申请日：2008-04-25

Applicant: Mayumi Nakasato ,  Hideki Mizuhara

Inventor： Mayumi Nakasato ,  Hideki Mizuhara

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element.

Abstract translation: 一种制造半导体模块的方法包括：在绝缘层的一个面上形成导体的第一工序; 使导体从绝缘层的另一面露出的第二工序; 在导体的暴露区域和绝缘层的另一面上设置第一布线层的第三工序; 制备其上形成有电路元件的基板的第四工序，在基板上形成第二布线; 以及在通过第三工序设置有第一布线层的导体的状态下，通过将绝缘层和基板压接而将导体埋入绝缘层中的第五工序与第二布线层相反。 形成接线而不会损坏电路元件。

公开(公告)号：US07405484B2

公开(公告)日：2008-07-29

申请号：US10951541

申请日：2004-09-28

Applicant: Ryosuke Usui ,  Hideki Mizuhara ,  Takeshi Nakamura

Inventor： Ryosuke Usui ,  Hideki Mizuhara ,  Takeshi Nakamura

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/244 ,  H05K3/305 ,  H05K3/3452 ,  H05K3/381 ,  H05K2201/0989 ,  H05K2203/049 ,  H05K2203/095 ,  Y10S438/906 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.

Abstract translation: 在电极膜上形成粘合膜，在其上形成涂膜。 镍，铬，钼，钨，铝或它们的合金被用作粘合膜的构成材料。 金，银，铂或它们的合金被用作涂膜的构成材料。

公开(公告)号：US20080023841A1

公开(公告)日：2008-01-31

申请号：US11830505

申请日：2007-07-30

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H01L23/48 ,  H01R12/04 ,  H05K3/02

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。