Abstract:
A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.
Abstract:
Microelectronic assemblies and methods of making the same are disclosed. In some embodiments, a microelectronic assembly includes a microelectronic element having edge surfaces bounding a front surface and contacts at the front surface; rigid metal posts disposed between at least one edge surface and a corresponding edge of the assembly, each metal post having a sidewall separating first and second end surfaces, the sidewalls have a root mean square (rms) surface roughness of less than about 1 micron; a encapsulation contacting at least the edge surfaces and the sidewalls; an insulation layer overlying the encapsulation; connection elements extending through the insulation layer, wherein at least some connection elements have cross sections smaller than those of the metal posts; a redistribution structure deposited on the insulation layer and electrically connecting first terminals with corresponding metal posts through the first connection elements, some metal posts electrically coupled with contacts of microelectronic element.
Abstract:
A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.
Abstract:
A method of forming a wire bond having a free end includes joining an end of a metal wire to a conductive element at a surface of a first component, the end of the metal wire being proximate a surface of a bonding tool adjacent an aperture through which the metal wire extends. A predetermined length of the metal wire is drawn out from the aperture. The surface of the bonding tool is used to plastically deform a region of the metal wire between the surface of the bonding tool and a metal element at the surface of the first component. The bonding tool then applies tension to the metal wire to cause a first portion of the metal wire having the end joined to the conductive element to detach from a remaining portion of the metal wire at the plastically deformed region.
Abstract:
Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements.
Abstract:
A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation.
Abstract:
High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.
Abstract:
A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts.
Abstract:
Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.
Abstract:
A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.