公开(公告)号：US20090200073A1

公开(公告)日：2009-08-13

申请号：US12203340

申请日：2008-09-03

Applicant: Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

Inventor： Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

IPC: H05K1/16 ,  G03F7/20 ,  H05K3/30

CPC classification number: H05K1/162 ,  H05K3/0044 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09845 ,  H05K2203/025 ,  H05K2203/1476

Abstract: A printed wiring board includes a capacitor including a dielectric body having a first surface and a second surface, a first electrode provided on the first surface of the dielectric body, and a second electrode provided on the second surface of the dielectric body. The first electrode has an area facing and being smaller than the first surface of the dielectric body, and the second electrode has an area facing and being larger than the second surface of the dielectric body.

Abstract translation: 印刷布线板包括电容器，其包括具有第一表面和第二表面的电介质体，设置在电介质体的第一表面上的第一电极和设置在电介质体的第二表面上的第二电极。 第一电极具有面向并小于电介质体的第一表面的面积，并且第二电极具有面向并大于电介质体的第二表面的面积。

公开(公告)号：US20090199399A1

公开(公告)日：2009-08-13

申请号：US12163252

申请日：2008-06-27

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K3/30

CPC classification number: H05K3/428 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01093 ,  H01L2924/14 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method for manufacturing a board with a built-in electronic element, includes providing a support substrate including a support base and a metal foil, forming a protective film made of a metal material on the metal foil of the support substrate, forming a conductive pattern made of a metal material on the protective film by an additive method, placing an electronic element on the support substrate with the conductive pattern such that a surface of the electronic element where a circuit is formed faces the conductive pattern, covering the electronic element with an insulative resin, etching away the metal foil using a first etching solution such that the protective film is not dissolved by the first etching solution or that the protective film has an etching speed which is slower than an etching speed of the metal foil, and electrically connecting terminals of the electronic element and a part of the conductive pattern.

Abstract translation: 一种用于制造具有内置电子元件的板的方法，包括提供包括支撑基底和金属箔的支撑基板，在支撑基板的金属箔上形成由金属材料制成的保护膜，形成导电图案 通过添加方法在保护膜上由金属材料制成，将电子元件放置在具有导电图案的支撑基板上，使得形成电路的电子元件的表面面向导电图案，用电子元件覆盖电子元件 绝缘树脂，使用第一蚀刻溶液蚀刻掉金属箔，使得保护膜不被第一蚀刻溶液溶解，或者保护膜具有比金属箔的蚀刻速度慢的蚀刻速度，并且电连接 电子元件的端子和导电图案的一部分。

公开(公告)号：US07525175B2

公开(公告)日：2009-04-28

申请号：US11341485

申请日：2006-01-30

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H01G2/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

Abstract translation: 当具有内置电容器的封装衬底包括通过高电介质层43中的针孔P彼此电短路的第一薄膜小电极41aa和第二薄膜小电极42aa时， 在第一薄膜小电极41aa中没有形成供电支柱61a和通孔61b，也不在第二薄膜小电极42aa中形成接地柱62a和通孔62b。 结果，短路的小电极41aa和42aa既不与电源线也不与接地线电连接，并且成为独立于电源电位和接地电位的电位。 因此，在薄膜电容器40中，只有短路的小电极41aa和42aa夹着高电介质层43的部分失去电容器功能，其他薄膜小电极41a和42a夹住高电介质的部分 层43保持电容器的功能。

公开(公告)号：US07495332B2

公开(公告)日：2009-02-24

申请号：US11563355

申请日：2006-11-27

Applicant: Takashi Kariya ,  Toshiki Furutani ,  Hirofumi Goto ,  Shin-ichiro Iwanaga

Inventor： Takashi Kariya ,  Toshiki Furutani ,  Hirofumi Goto ,  Shin-ichiro Iwanaga

IPC: H01L23/14 ,  H01L23/28

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674

Abstract: A multilayer printed wiring board is equipped with a core board 20, a build-up layer 30 formed on the core board 20 so as to have a conductor pattern 32 on the upper surface thereof, a low-elasticity layer 40 formed on the build-up layer 30, lands 52 that are provided on the upper surface of the low-elasticity layer 40 and connected to an IC chip 70 via solder bumps 66, and conductor posts 50 that penetrate through the low-elasticity layer 40 and electrically connect the lands 52 to the conductor pattern 32. The low-elasticity layer 40 is formed of resin composition containing epoxy resin, phenol resin, cross-linked rubber particles and a hardening catalyst.

Abstract translation: 多层印刷电路板配备有芯板20，形成在芯板20上的积层30，以在其上表面具有导体图案32，形成在构建层20上的低弹性层40， 上层30，设置在低弹性层40的上表面上并通过焊锡凸块66连接到IC芯片70的焊盘52以及穿过低弹性层40并导电连接焊盘的导体柱50 低弹性层40由包含环氧树脂，酚醛树脂，交联橡胶颗粒和硬化催化剂的树脂组合物形成。

公开(公告)号：US07489521B2

公开(公告)日：2009-02-10

申请号：US11778989

申请日：2007-07-17

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board (10) includes: a build-up layer (30) that is formed on a core substrate (20) and has a conductor pattern (32) disposed on an upper surface; a low elastic modulus layer (40) that is formed on the build-up layer (30); lands (52) that are disposed on an upper surface of the low elastic modulus layer (40) and connected via solder bumps (66) to a IC chip (70); and conductor posts (50) that pass through the low elastic modulus layer (40) and electrically connect lands (52) with conductor patterns (32). The conductor posts (50) have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer (40), is greater than or equal to the aspect ratio Rasp of internal conductor posts (50b), which are positioned at internal portions of the low elastic modulus layer (40).

Abstract translation: 多层印刷布线板（10）包括：形成在芯基板（20）上并具有布置在上表面上的导体图案（32）的堆积层（30） 形成在积层（30）上的低弹性模量层（40）; 设置在低弹性模量层（40）的上表面并通过焊锡凸块（66）连接到IC芯片（70）的平台（52）; 以及穿过低弹性模量层（40）并将焊盘（52）与导体图案（32）电连接的导体柱（50）。 导体柱50具有不小于4的纵横比Rasp（高度/最小直径）和最小直径超过30μm，并且外部导体柱50a的纵横比Rasp位于低的外部 弹性模量层（40）大于或等于位于低弹性模量层（40）的内部的内部导体柱（50b）的纵横比Rasp。

公开(公告)号：US07462784B2

公开(公告)日：2008-12-09

申请号：US11415117

申请日：2006-05-02

Applicant: Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

Inventor： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC: H05K1/16

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: This invention provides a multilayer printed wiring board which achieves fine pitches. A heat resistant substrate is incorporated in a multilayer printed wiring board and interlayer resin insulation layer and conductive layer are placed alternately on the heat resistant substrate. A built-up wiring board in which respective conductive layers are connected by via hole is formed. A via hole is formed on the surface of a mirror-processed Si substrate by using a heat resistant substrate composed of Si substrate so that finer wiring than a resin substrate having unevenness in its surface can be formed, whereby achieving fine pitches. Further, by forming the wiring on a mirror processed surface, dispersion of wiring decreases thereby decreasing dispersion of impedance.

Abstract translation: 本发明提供一种实现细小间距的多层印刷线路板。 在多层印刷线路板和层间树脂绝缘层中并入耐热基板，并将导电层交替放置在耐热基板上。 形成各导电层通过通孔连接的叠层布线板。 通过使用由Si衬底构成的耐热衬底，在镜面处理的Si衬底的表面上形成通孔，从而可以形成比其表面不均匀的树脂衬底更细的布线，从而实现细小的间距。 此外，通过在镜面处理表面上形成布线，布线的分散减小，从而减小阻抗的分散。

公开(公告)号：US20080024953A1

公开(公告)日：2008-01-31

申请号：US11495668

申请日：2006-07-31

Applicant: Hajime Sakamoto ,  Takashi Kariya ,  Yasuhiko Mano

Inventor： Hajime Sakamoto ,  Takashi Kariya ,  Yasuhiko Mano

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G2/06 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2203/171

Abstract: The capacitance of a capacitor is adjusted by forming openings in one of a pair of electrodes of the capacitor, the openings having different sizes d1, d2, d3, wherein d1>d2>d3> . . . and being arranged in numbers n1, n2, n3, . . . , respectively; and sequentially filling a necessary number of the openings with an electroconductive material in descending order of the size so as to adjust the capacitance gradually with an increasing degree of precision. The resulting capacitor is mounted to a printed wiring board.

Abstract translation: 通过在电容器的一对电极中的一个电极中形成开口来调节电容器的电容，开口具有不同的尺寸d 1，d 2，d 3，其中d 1> d 2> d 3>。 。 。 并且以n 1，n 2，n 3，...排列。 。 。 ， 分别; 并按照大小的降序顺序地用导电材料填充必要数量的开口，以随着精度的增加逐渐调整电容。 所得到的电容器安装到印刷线路板上。

公开(公告)号：US20070187140A1

公开(公告)日：2007-08-16

申请号：US11566912

申请日：2006-12-05

Applicant: Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

Inventor： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC: H05K1/16

CPC classification number: H05K3/326 ,  H01L23/49811 ,  H01L24/72 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/28 ,  H05K3/341 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0314 ,  H05K2201/0397 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention is to provide a printed wiring board in which malconnection or disconnection caused by a difference between coefficients of thermal expansion of a semiconductor chip and a printed wiring board can be decreased even when a highly-integrated semiconductor apparatus is mounted thereon and an electronic device using the same. An electronic device (4) according to the present invention includes a printed wiring board (1) with a component mounting pin (18) and a surface-mounting type semiconductor apparatus (2) with an electrode pad (3), wherein the component mounting pin (18) has elasticity and is urged against the electrode pad (3) to maintain electric connection.

Abstract translation: 本发明是提供一种印刷电路板，其中即使在高度集成的半导体装置安装在其上时也能够降低由半导体芯片和印刷电路板的热膨胀系数之间的差异引起的故障连接或断开，并且电子 设备使用相同。 根据本发明的电子设备（4）包括具有元件安装销（18）的印刷电路板（1）和具有电极焊盘（3）的表面安装型半导体设备（2），其中元件安装 销（18）具有弹性并且被推靠在电极焊盘（3）上以保持电连接。

公开(公告)号：US20070132088A1

公开(公告)日：2007-06-14

申请号：US11580928

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H01L23/04

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US20060237225A1

公开(公告)日：2006-10-26

申请号：US10546620

申请日：2004-02-05

Applicant: Takashi Kariya ,  Akiyoshi Tsuda

Inventor： Takashi Kariya ,  Akiyoshi Tsuda

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H01L24/06 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2203/049 ,  H05K2203/0733 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: In a multi-layer printed wiring board 100 comprising single side circuit boards A, B and for accommodating an IC chip 70, BGAs 56 are disposed on its front and rear faces, so that with an IC module 120 mounted through the BGA 56 on the front face, this board can be connected to a printed wiring board through the BGA 56 on the rear face. Thus, freedom in the configuration of the IC module mounted increases so that various kinds of the IC modules can be loaded.

Abstract translation: 在包括单侧电路板A，B并且用于容纳IC芯片70的多层印刷线路板100中，在其前表面和后表面上布置有BGA 56，使得通过在BGA 56上安装的IC模块120 正面，该板可以通过后面的BGA 56连接到印刷电路板。 因此，安装的IC模块的结构自由度增加，从而可以加载各种IC模块。