公开(公告)号：US20240222280A1

公开(公告)日：2024-07-04

申请号：US18363995

申请日：2023-08-02

申请人： Samsung Electronics Co., Ltd.

发明人： MyungDo CHO ,  Youngchan KO ,  Gyeongho KIM ,  Byung Ho KIM ,  Yongkoon LEE ,  Jeongho LEE

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/182

摘要： A semiconductor package may include: a first redistribution layer structure; a bridge structure on the first redistribution layer structure; a plurality of conductive pillars on the first redistribution layer structure and side by side with the bridge structure; an encapsulant molding the bridge structure and the plurality of conductive pillars on the first redistribution layer structure; a second redistribution layer structure on the encapsulant, wherein a region of the second redistribution layer structure on the bridge structure is defined as a first region and a region other than the first region is defined as a second region; and a plurality of bonding pads at the first region. A vertical thickness of the first region may be smaller than a vertical thickness of the second region.

公开(公告)号：US20240213217A1

公开(公告)日：2024-06-27

申请号：US18086575

申请日：2022-12-21

申请人： International Business Machines Corporation

发明人： David Michael Audette ,  Grant Wagner ,  Steven Paul Ostrander ,  Hubert Harrer ,  Arvind Kumar ,  Thomas Anthony Wassick ,  Matthew Sean Grady ,  Sungjun Chun

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/0655 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/1412 ,  H01L2224/16227

摘要： An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.

公开(公告)号：US20240213198A1

公开(公告)日：2024-06-27

申请号：US18087517

申请日：2022-12-22

申请人： Intel Corporation

发明人： Liang He ,  Yue Deng ,  Gang Duan ,  Jung Kyu Han ,  Ali Lehaf ,  Srinivas Pietambaram

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L24/13 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13541 ,  H01L2224/1358 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13684 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

摘要： An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

公开(公告)号：US20240213167A1

公开(公告)日：2024-06-27

申请号：US18432353

申请日：2024-02-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Kai CHENG ,  Tsung-Shu LIN ,  Tsung-Yu CHEN ,  Hsien-Pin HU ,  Wen-Hsin WEI

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/5384 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/24225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058

摘要： A package structure and method for forming the same are provided. The package structure includes a substrate having a front surface and a back surface, and a die formed on the back surface of the substrate. The package structure includes a first through via structure formed in the substrate, a conductive structure formed in a passivation layer) over the front surface of the substrate. The conductive structure includes a via portion in direct contact with the substrate. The package structure includes a connector (formed over the via portion, wherein the connector includes an extending portion directly on a recessed top surface of the via portion.

公开(公告)号：US20240213073A1

公开(公告)日：2024-06-27

申请号：US18424790

申请日：2024-01-27

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US12021045B2

公开(公告)日：2024-06-25

申请号：US18186348

申请日：2023-03-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC分类号： H01L23/66 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28 ,  H01Q21/06

CPC分类号： H01L23/66 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01Q1/2283 ,  H01Q9/045 ,  H01Q9/285 ,  H01Q21/062 ,  H01Q21/065 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US12021042B2

公开(公告)日：2024-06-25

申请号：US18187662

申请日：2023-03-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC分类号： H01L25/16 ,  H01L21/50 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065

CPC分类号： H01L23/552 ,  H01L21/50 ,  H01L23/16 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/165 ,  H01L2224/08113 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32245 ,  H01L2924/16195

摘要： A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

公开(公告)号：US12021037B2

公开(公告)日：2024-06-25

申请号：US18077778

申请日：2022-12-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/17 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/81815 ,  H01L2924/00014

摘要： Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

公开(公告)号：US20240204083A1

公开(公告)日：2024-06-20

申请号：US18066307

申请日：2022-12-15

申请人： Intel Corporation

发明人： Gurpreet Singh ,  Manish Chandhok ,  Florian Gstrein ,  Charles Henry Wallace ,  Eungnak Han ,  Leonard P. Guler

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L29/6656 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L29/66545 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2924/15311

摘要： DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.

公开(公告)号：US20240203942A1

公开(公告)日：2024-06-20

申请号：US18354928

申请日：2023-07-19

申请人： Samsung Electronics Co., Ltd.

发明人： Doyoung Jang ,  Eunsu Lee ,  Daeyoung Jung

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

CPC分类号： H01L25/0655 ,  H01L23/481 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/48229 ,  H01L2924/1431 ,  H01L2924/1434

摘要： A semiconductor package includes a first substrate, a first semiconductor chip on the first substrate, and second semiconductor chips on the first substrate and adjacent sides of the first semiconductor chip, each of the second semiconductor chips has an elongated shape extending along one of the sides of the first semiconductor chip which is adjacent thereto, and a width of each of the second semiconductor chips is smaller than a width of the first semiconductor chip.