公开(公告)号：US09564362B2

公开(公告)日：2017-02-07

申请号：US14615077

申请日：2015-02-05

申请人： International Business Machines Corporation

发明人： Brett C. Baker-O'Neal ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC分类号： H01L21/76892 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53295

摘要： A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.

摘要翻译： 一种用于在集成电路中形成至少一种Ag或Ag基合金特征的方法，包括在基底上以多层结构提供Ag或Ag基合金的覆盖层。 该方法还包括在Ag或Ag基合金的覆盖层上提供硬掩模层。 该方法还包括对Ag或Ag基合金的覆盖层进行蚀刻，其中在蚀刻后保留的Ag或Ag基合金的覆盖层的一部分形成一个或多个导电线。 所述方法还包括形成围绕所述一条或多条导电线的衬里。 该方法还包括在多层结构上沉积介电层。

公开(公告)号：US09536783B2

公开(公告)日：2017-01-03

申请号：US14591566

申请日：2015-01-07

申请人： Cree, Inc.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz ,  Van Mieczkowski

IPC分类号： H01L21/283 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L21/3213

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US09520558B2

公开(公告)日：2016-12-13

申请号：US13961479

申请日：2013-08-07

申请人： Micron Technology, Inc.

发明人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC分类号： H01L45/00 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

摘要翻译： 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US09425090B2

公开(公告)日：2016-08-23

申请号：US14491470

申请日：2014-09-19

申请人： Infineon Technologies Austria AG

发明人： Arno Zechmann

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/53252 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer. The seed includes a noble metal other than gold. The substrate is masked so that a first mask opening is laterally aligned with the first terminal. An unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure in the first mask opening. The mask, the masked portions of the seed layer, and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer.

摘要翻译： 导电阻挡层形成在半导体衬底上，使得阻挡层覆盖第一器件端子。 种子层形成在阻挡层上。 种子包括除金以外的贵金属。 掩模基板，使得第一掩模开口与第一端子横向对齐。 使用金电解质溶液电镀种籽层的未掩蔽部分，以在第一掩模开口中形成第一金金属化结构。 除去掩模，种子层的掩蔽部分和阻挡层。 来自种子层的未掩蔽部分的贵金属被扩散到第一金金属化结构中。 第一金金属化结构经由阻挡层电连接到第一端子。

公开(公告)号：US09416004B2

公开(公告)日：2016-08-16

申请号：US14595543

申请日：2015-01-13

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Guangcai Fu ,  Tianlun Yang ,  Xiaoping Zhang

IPC分类号： H01L21/44 ,  B81C1/00 ,  H01L21/475

CPC分类号： H01L23/5283 ,  B81B7/007 ,  B81B2201/0264 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00849 ,  B81C2201/0132 ,  H01L21/02068 ,  H01L21/475 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53247 ,  H01L29/0649 ,  H01L2221/1063

摘要： Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process.

摘要翻译： 提供了半导体器件和制造方法。 在半导体器件中，半导体衬底包括具有与半导体衬底的顶表面共面的顶表面的第一电极层。 在半导体衬底和第一电极层上形成牺牲层。 在牺牲层上形成由导电材料制成的第一掩模层。 蚀刻第一掩模层和牺牲层直到暴露第一​​电极层的表面以形成穿过第一掩模层和牺牲层的开口。 执行清洁处理以去除粘附到第一掩模层的表面并附着到开口的侧壁和底表面上的蚀刻副产物。 在清洁过程之后，在开口中形成导电塞。

公开(公告)号：US20150364462A1

公开(公告)日：2015-12-17

申请号：US14837153

申请日：2015-08-27

申请人： Murata Manufacturing Co., Ltd.

发明人： TOSHIYUKI NAKAISO ,  Noboru Kato

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L23/485 ,  H01L23/3192 ,  H01L23/4824 ,  H01L23/4827 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53247 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/05 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/0814 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2924/0504

摘要： An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

摘要翻译： 一种ESD保护装置，包括形成在所述基板的表面的具有ESD保护电路的Si衬底; 在Si衬底上形成的焊盘; 与Si衬底的表面相对的再布线层，其包括电连接到焊盘的端子电极。 重新配线层包括形成在Si衬底的表面上的SiN保护膜，以覆盖与形成在树脂层中的开口（接触孔）接触的区域之外的部分焊盘，并且介电常数低于 SiN保护膜，并形成在SiN保护膜和端子电极之间。 因此，提供了可以减少寄生电容的产生并且消除所产生的寄生电容的变化的半导体器件。

公开(公告)号：US08933543B2

公开(公告)日：2015-01-13

申请号：US13503972

申请日：2011-03-15

申请人： Toshiya Yokogawa ,  Mitsuaki Oya ,  Atsushi Yamada ,  Akihiro Isozaki

发明人： Toshiya Yokogawa ,  Mitsuaki Oya ,  Atsushi Yamada ,  Akihiro Isozaki

IPC分类号： H01L33/16 ,  H01L21/02 ,  H01L33/40 ,  H01L23/532 ,  H01L33/00 ,  H01L33/32 ,  H01S5/042 ,  H01S5/32 ,  H01S5/323

CPC分类号： H01L21/02579 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L23/53247 ,  H01L33/0075 ,  H01L33/16 ,  H01L33/32 ,  H01L33/40 ,  H01L2224/13 ,  H01L2924/12032 ,  H01L2933/0016 ,  H01S5/0425 ,  H01S5/3202 ,  H01S5/32341 ,  H01L2924/00

摘要： A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x≧0, y≧0, and z≧0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.

摘要翻译： 本发明的氮化物系半导体器件包括：氮化物系半导体多层结构体20，其具有p型半导体区域，表面12从m面倾斜不小于1°的角度， 超过5°; 以及设置在p型半导体区域上的电极30。 p型半导体区域由Al x In y Ga z N（其中x + y + z = 1，x≥0，y≥0和z≥0）层26形成。电极30包括Mg层32和Ag层34 设置在Mg层32上.Mg层32与半导体多层结构体20的p型半导体区域的表面12接触。

公开(公告)号：US08637957B1

公开(公告)日：2014-01-28

申请号：US13552293

申请日：2012-07-18

申请人： Chih-Chao Yang ,  Stephen M. Gates

发明人： Chih-Chao Yang ,  Stephen M. Gates

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  G11C17/165 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53247 ,  H01L23/5329 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.

摘要翻译： 提供一种抗熔丝结构，其中抗熔丝材料衬垫嵌入设置在互连电介质材料内的一个开口内。 反熔丝材料衬垫位于第一导电金属和第二导电金属之间，第一导电金属和第二导电金属也存在于开口内。 扩散阻挡衬里将第一导电金属与互连电介质材料的任何部分分开。 反熔丝结构横向邻近形成在与反熔丝结构相同的互连电介质材料内的互连结构。

公开(公告)号：US20110310322A1

公开(公告)日：2011-12-22

申请号：US13219814

申请日：2011-08-29

申请人： Kazuyoshi INOUE ,  Shigekazu Tomai ,  Masato Matsubara

发明人： Kazuyoshi INOUE ,  Shigekazu Tomai ,  Masato Matsubara

IPC分类号： G02F1/136 ,  H01L33/08 ,  H01L21/283 ,  H01L29/786

CPC分类号： H01L29/78696 ,  C04B35/01 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3251 ,  C04B2235/3256 ,  C04B2235/3258 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3287 ,  C04B2235/3289 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/77 ,  C23C14/08 ,  C23C14/3414 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  H01L23/53219 ,  H01L23/53247 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a thin film transistor substrate having a transparent electroconductive film in which residues and so on resulting etching are hardly generated; a process for producing the same; and a liquid crystal display using this thin film transistor substrate.A thin film transistor substrate, comprising a transparent substrate, a source electrode formed over the transparent substrate, a drain electrode formed over the transparent substrate, and a transparent pixel electrode formed over the transparent substrate, wherein the transparent pixel electrode is a transparent electroconductive film which is made mainly of indium oxide, and further comprises one or two or more oxides selected from tungsten oxide, molybdenum oxide, nickel oxide and niobium oxide, and the transparent pixel electrode is electrically connected to the source electrode or the drain electrode; a process for producing the same; and a liquid crystal display using this thin film transistor substrate.

摘要翻译： 提供了具有透明导电膜的薄膜晶体管基板，其中几乎不产生所得到的蚀刻残留物等; 其制造方法; 以及使用该薄膜晶体管基板的液晶显示器。 一种薄膜晶体管基板，包括透明基板，形成在所述透明基板上的源电极，形成在所述透明基板上的漏电极和形成在所述透明基板上的透明像素电极，其中所述透明像素电极是透明导电膜 其主要由氧化铟制成，并且还包含一种或两种以上选自氧化钨，氧化钼，氧化镍和氧化铌的氧化物，透明像素电极与源电极或漏电极电连接; 其制造方法; 以及使用该薄膜晶体管基板的液晶显示器。

公开(公告)号：US20110127563A1

公开(公告)日：2011-06-02

申请号：US12854278

申请日：2010-08-11

申请人： Hsiu Jen Lin ,  Jian Shian Lin ,  Shau Yi Chen ,  Chieh Lung Lai

发明人： Hsiu Jen Lin ,  Jian Shian Lin ,  Shau Yi Chen ,  Chieh Lung Lai

IPC分类号： H01L33/62 ,  H01L21/50

CPC分类号： H01L23/53247 ,  H01L24/29 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/30 ,  H01L33/40 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/83193 ,  H01L2224/83207 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00014

摘要： A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.

摘要翻译： 芯片接合方法适合于将具有第一金属薄膜层的LED芯片芯片接合到基板上。 该方法包括在基板的表面上形成第二金属薄膜层; 在所述第二金属薄膜层上形成芯片接合材料层; 将第一金属薄膜层与芯片接合材料层接触，将LED芯片放置在芯片接合材料层上; 在液固固体反应温度下加热芯片接合材料层预固化时间，以形成第一金属间层和第二金属间层; 并在固 - 固反应温度下加热芯片接合材料层达固化时间，以进行固 - 固反应。 液固反应温度和固 - 固反应温度均低于110℃，固 - 固反应后第一和第二金属间化合物的熔点高于200℃。