公开(公告)号：US20180248092A1

公开(公告)日：2018-08-30

申请号：US15900685

申请日：2018-02-20

Applicant: Jen-You Liang

Inventor： Jen-You Liang

IPC: H01L33/62 ,  H01L33/60 ,  H05K1/03 ,  H05K1/18

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/60 ,  H05K1/03 ,  H05K1/05 ,  H05K1/181 ,  H05K3/0052 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10227 ,  H05K2201/10522 ,  H05K2201/1053

Abstract: A light sensor lead frame substrate may comprise a plurality of lead frame substrates formed on a metal substrate through a series of processing including chemical etching, plasma etching and stamping. The lead frame substrates are connected through a plurality of connecting sections, and each of the lead frame substrates is connected to the metal substrate through the connecting section. Each of the connecting sections has two pre-cut sections respectively formed at two ends of the connecting section. After molding, the lead frame substrates are configured to pass through a series of processing including electroplating, injection and desmear to enable each of the lead frame substrates to have a first insulating layer, a reflector cup and a second insulating layer, and with the pre-cut sections, the connecting sections are adapted to be easily washed down by a punch in the punching process.

公开(公告)号：US20180240756A1

公开(公告)日：2018-08-23

申请号：US15753426

申请日：2016-08-30

Applicant: 3M INNOVATIVE PROPERTIES COMPANY

Inventor： Siang Sin Foo ,  Hiromitsu Kosugi ,  Alejandro Aldrin A. Narag, II ,  Ravi Palaniswamy

IPC: H01L23/544 ,  H01L23/498 ,  H01L33/62 ,  H01L21/48

CPC classification number: H01L23/544 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L33/62 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/81132 ,  H01L2224/81385 ,  H01L2224/83132 ,  H01L2224/83385 ,  H01L2224/85132 ,  H01L2224/85385 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2933/0066 ,  H05K1/0269 ,  H05K1/111 ,  H05K1/189 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/09918 ,  H05K2201/10106 ,  H01L2224/45099 ,  H01L2924/014

Abstract: A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first and second electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within the LESD mounting region.

公开(公告)号：US09826639B2

公开(公告)日：2017-11-21

申请号：US15351814

申请日：2016-11-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tatsuaki Denda ,  Osamu Hoshino

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/113 ,  H01L23/49534 ,  H05K1/181 ,  H05K3/005 ,  H05K3/244 ,  H05K3/3431 ,  H05K3/427 ,  H05K3/428 ,  H05K2201/09563 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10234 ,  H05K2201/10545 ,  H05K2203/0733

Abstract: A wiring substrate includes an insulating layer, a first wiring layer and a second wiring layer on opposite sides of the insulating layer, and a via piercing through the first wiring layer and the insulating layer to electrically connect to the second wiring layer. The via includes an end portion projecting from a first surface of the first wiring layer facing away from the insulating layer. A surface of the end portion facing in the same direction as the first surface of the first wiring layer is depressed to be deeper in the center than in the periphery.

公开(公告)号：US20170328392A1

公开(公告)日：2017-11-16

申请号：US15595631

申请日：2017-05-15

Applicant: Kathrein Werke KG

Inventor： Jörg Langenberg ,  Florian Leinenbach ,  Philipp Ponn

IPC: F16B5/00 ,  F16B5/02

CPC classification number: F16B5/0024 ,  F16B5/02 ,  H01Q21/08 ,  H01Q21/26 ,  H05K3/0061 ,  H05K3/3447 ,  H05K9/006 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09072 ,  H05K2201/093 ,  H05K2201/09718 ,  H05K2201/09745 ,  H05K2201/10371 ,  H05K2201/2036

Abstract: What is provided is an adapter plate for HF structures, which is set up for being disposed between a back of a circuit board and a reflector, wherein the adapter plate is electrically conductive, and the adapter plate has an opening or a cavity at every location where an element is passed through the circuit board to the side of the adapter plate, wherein at least one element is passed through the circuit board exclusively for ground contacting.

公开(公告)号：US20170265299A1

公开(公告)日：2017-09-14

申请号：US15452775

申请日：2017-03-08

Applicant: IBIDEN CO., LTD.

Inventor： Katsutoshi KITAGAWA

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K1/111 ,  H05K1/028 ,  H05K1/118 ,  H05K3/0011 ,  H05K3/281 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10416 ,  Y02P70/611

Abstract: A wiring board includes a substrate, a surface protection film laminated on the substrate and having an opening portion, and a conductor block embedded in the substrate and having a pad portion exposed by the opening portion of the surface protection film. The conductor block has an annular groove formed such that the annular groove is surrounding the pad portion of the conductor block, and the surface protection film is formed such that a portion of the surface protection film is extending into the annular groove.

公开(公告)号：US20170156213A1

公开(公告)日：2017-06-01

申请号：US15358948

申请日：2016-11-22

Applicant: CANON KABUSHIKI KAISHA

Inventor： Koji Ishikawa

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3421 ,  H01R4/023 ,  H01R11/11 ,  H05K1/111 ,  H05K1/18 ,  H05K2201/09381 ,  H05K2201/09745 ,  H05K2201/10287 ,  Y02P70/613

Abstract: A wiring board and an electronic device which suppress variation in a leading direction of lead wire after soldering and variation in a tip position of the lead wire and keep a height of a soldered lead wire low while suppressing variation in the height. A wiring board is soldered with lead wire. A surface of the wiring board is formed with a land part by exposing a conductor. The land part is formed with a groove part, which is a region not including the conductor, for positioning of the lead wire along a leading direction. The lead wire mounted to the groove part is soldered to the land part in such a manner as to cover the groove part.

公开(公告)号：US09504152B2

公开(公告)日：2016-11-22

申请号：US14748970

申请日：2015-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hai Liu

IPC: H05K1/11 ,  H01L23/498 ,  H05K3/46 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/244 ,  H05K3/46 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A printed circuit board for a semiconductor package including a printed circuit board body, a plurality of ball lands on one surface of the printed circuit board body, a first plating layer on a portion of each of the ball lands, and a second plating layer on another portion of each of the ball lands may be provided. An upper surface of the first plating layer may be coplanar with an upper surface of the second plating layer.

Abstract translation: 一种用于半导体封装的印刷电路板，包括印刷电路板主体，印刷电路板主体的一个表面上的多个球形区域，每个球场的一部分上的第一镀层和第二镀层 可以设置每个球场的另一部分。 第一镀层的上表面可以与第二镀层的上表面共面。

公开(公告)号：US09338880B2

公开(公告)日：2016-05-10

申请号：US13484719

申请日：2012-05-31

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US20160095222A1

公开(公告)日：2016-03-31

申请号：US14866073

申请日：2015-09-25

Applicant: Point Engineering Co., Ltd.

Inventor： Seung Ho Park ,  Tae Hwan Song ,  Sung Hyun Byun

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/60 ,  H05K1/05 ,  H05K1/185 ,  H05K2201/09745 ,  H05K2201/10106

Abstract: A chip substrate includes conductive portions, an insulation portion and a cavity. The conductive portions are laminated in one direction to constitute the chip substrate. The insulation portion is interposed between the conductive portions to electrically isolate the conductive portions. The cavity is formed on an upper surface of the chip substrate at a predetermined depth in a region including the insulation portion. The cavity is defined by a plurality of continuously-extending curved surfaces having predetermined radii of curvature.

Abstract translation: 芯片基板包括导电部分，绝缘部分和空腔。 导电部分沿一个方向层叠以构成芯片基板。 绝缘部分介于导电部分之间，以使导电部分电隔离。 在包括绝缘部分的区域中，在芯片基板的上表面上以预定的深度形成空腔。 空腔由具有预定曲率半径的多个连续延伸的弯曲表面限定。

公开(公告)号：US20150351223A1

公开(公告)日：2015-12-03

申请号：US14728125

申请日：2015-06-02

Applicant: SUMITOMO BAKELITE CO., LTD.

Inventor： Yoshihide Nii ,  Toshio Komiyatani ,  Yukiharu Yuzuriha

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/05 ,  H05K2201/09745 ,  H05K2201/10166

Abstract: The metal-based mounting board includes: a metal-based circuit board including a metal substrate having a first surface and a second surface, an insulating film provided on the first surface and a metal film provided on the insulating film; and an electronic component provided on the metal film of the metal-based circuit board. Within the metal substrate, a region which overlaps with a collection of a plurality of lines each having an angle of 45° or less with respect to a normal line of the metal-based mounting board, the lines each passing through a surface of the electronic component facing the metal film, is defined as a first region. A region other than the first region is defined as a second region. At least one groove is provided within the first region so as to surround the electronic component in a planar view of the metal-based mounting board.

Abstract translation: 金属基安装板包括：金属基电路板，包括具有第一表面和第二表面的金属基板，设置在第一表面上的绝缘膜和设置在绝缘膜上的金属膜; 以及设置在金属基电路板的金属膜上的电子部件。 在金属基板内，与金属基安装基板的法线相比，重叠于多个相互成45度以下的角度的集合的区域，各条线通过电子表面 面向金属膜的部件被定义为第一区域。 除了第一区域之外的区域被定义为第二区域。 在第一区域内设置至少一个凹槽，以便在金属基安装板的平面视图中围绕电子部件。