公开(公告)号：US08664043B2

公开(公告)日：2014-03-04

申请号：US12628428

申请日：2009-12-01

Applicant: Henrik Ewe ,  Joachim Mahler ,  Anton Prueckl ,  Stefan Landau

Inventor： Henrik Ewe ,  Joachim Mahler ,  Anton Prueckl ,  Stefan Landau

IPC: H01L21/44

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/05 ,  H05K1/185 ,  H05K1/188 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K2203/0353 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

Abstract translation: 公开了一种制造层压电子装置的方法。 一个实施例提供载体，载体限定第一主表面和与第一主表面相对的第二主表面。 载体具有形成在第一主表面中的凹陷图案。 第一半导体芯片附接在第一和第二主表面之一上。 覆盖在其上附着有第一半导体芯片的载体的主表面上的第一绝缘层和形成第一半导体芯片。 然后沿着凹槽图案将载体分离成多个部分。

公开(公告)号：US08633591B2

公开(公告)日：2014-01-21

申请号：US13712224

申请日：2012-12-12

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。

公开(公告)号：US20130344716A1

公开(公告)日：2013-12-26

申请号：US13919243

申请日：2013-06-17

Applicant: TELLABS OY

Inventor： Alf BJORKLOF ,  Antti HOLMA

IPC: H01R13/04 ,  H01R43/20

CPC classification number: H01R13/04 ,  H01R43/205 ,  H05K3/222 ,  H05K3/306 ,  H05K2201/09972 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10363 ,  H05K2201/10446 ,  H05K2201/1059 ,  H05K2201/2018 ,  H05K2203/162 ,  Y10T29/49004 ,  Y10T29/4913

Abstract: A method for manufacturing a circuit board system includes attaching (501), to a circuit board, electrical components that constitute together with the circuit board a first functional entity and a second functional entity that are disconnected from each other so that operations of the first and second functional entities are substantially free from mutual interactions. The method includes directing (502) electrical activity, for example testing and/or data loading, to the first functional entity and/or to the second functional entity. Subsequently, the method includes providing (503) at least one galvanic connection between the first and second functional entities by pushing one or more press-fit pins in holes of the circuit board in order to enable the first and second functional entities to co-operate with each other. The method allows functional entity-specific testing, data loading, and other electrical activity after e.g. a soldering process and prior to possible functionality testing (504).

Abstract translation: 一种用于制造电路板系统的方法，包括：将与所述电路板一起构成的第一功能实体和第二功能实体与电路板连接（501），所述第一功能实体和第二功能实体彼此断开连接，使得所述第一和第 第二功能实体基本上没有相互作用。 该方法包括将电活动（例如测试和/或数据加载）引导（502）到第一功能实体和/或第二功能实体。 随后，该方法包括在第一和第二功能实体之间提供（503）至少一个电流连接，通过将一个或多个压配合引脚推入电路板的孔中，以使第一和第二功能实体能够合作 与彼此。 该方法允许功能实体特异性测试，数据加载和其他电活动。 焊接过程和可能的功能测试之前（504）。

公开(公告)号：US20130333928A1

公开(公告)日：2013-12-19

申请号：US13495372

申请日：2012-06-13

Applicant: Don A. Gilliland ,  Dennis J. Wurth

Inventor： Don A. Gilliland ,  Dennis J. Wurth

IPC: H05K1/11 ,  H05K3/10 ,  H05K1/09

CPC classification number: H05K1/0231 ,  H05K1/0233 ,  H05K1/11 ,  H05K2201/086 ,  H05K2201/09972 ,  Y10T29/49155

Abstract: Methods and structures are provided for implementing feed-through and domain isolation using ferrite and containment barriers. A vertical isolator is provided between a first domain and a second domain on a printed circuit board with signals passing between the first domain and the second domain. The vertical isolator is placed over a domain separation gap between the first and second domains in the printed circuit board, the vertical isolator having a vertical isolation barrier between a first vertical plate coupled to the first domain and a second vertical plate coupled to the second domain. The vertical isolation barrier is formed of a unitary ferrite block or a non-conductive magnetic absorber material. A plurality of capacitance feed-through plates and a dielectric material are provided within the vertical isolator.

Abstract translation: 提供了方法和结构，用于实施使用铁素体和遏制屏障的馈通和区域隔离。 垂直隔离器设置在印刷电路板上的第一域和第二域之间，信号通过第一域与第二域之间。 垂直隔离器放置在印刷电路板中的第一和第二畴之间的畴分离间隙上，垂直隔离器在耦合到第一域的第一垂直板和耦合到第二域的第二垂直板之间具有垂直隔离屏障 。 垂直隔离屏障由单一铁氧体块或非导电磁性吸收材料形成。 在垂直隔离器内提供多个电容馈通板和电介质材料。

公开(公告)号：US20130269982A1

公开(公告)日：2013-10-17

申请号：US13446783

申请日：2012-04-13

Applicant: Dejan Teofilovic

Inventor： Dejan Teofilovic

IPC: H01B17/60

CPC classification number: H05K1/0256 ,  H05K1/0227 ,  H05K2201/0761 ,  H05K2201/09781 ,  H05K2201/09972 ,  H05K2201/10121

Abstract: An electrical circuit with large creepage isolation distances is provided. In some embodiments, the electrical circuit is capable of increasing creepage isolation distances by many multiples over traditional electrical circuits. In one embodiment, an electrical circuit comprises a ground circuit optically coupled to a floating circuit, and an isolated circuit optically coupled to the floating circuit. The circuits can be optically coupled with opto-isolators, for example. The isolated circuit can have a creepage isolation distance at least twice as large as a traditional circuit. In some embodiments, “n” number of floating circuits can be optically coupled between the ground circuit and the isolated circuit to increase the total creepage isolation distance by a factor of “n”. Methods of use are also described.

Abstract translation: 提供了具有大爬电隔离距离的电路。 在一些实施例中，电路能够在传统电路上增加多个倍数的爬电隔离距离。 在一个实施例中，电路包括光耦合到浮置电路的接地电路和与浮动电路光耦合的隔离电路。 例如，电路可以与光隔离器光学耦合。 隔离电路的爬电隔离距离至少为传统电路的两倍。 在一些实施例中，“n”个浮动电路可以在接地电路和隔离电路之间光学耦合，以将总爬电隔离距离提高因子“n”。 还描述了使用方法。

公开(公告)号：US20130227838A1

公开(公告)日：2013-09-05

申请号：US13859421

申请日：2013-04-09

Applicant: David Shykind ,  James McCall

Inventor： David Shykind ,  James McCall

IPC: H05K3/10

CPC classification number: H05K3/10 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0366 ,  H05K3/0052 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09972 ,  H05K2203/1554 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49798 ,  Y10T428/24058 ,  Y10T428/24917 ,  Y10T428/249935 ,  Y10T428/24994 ,  Y10T428/249943 ,  Y10T428/249946 ,  Y10T442/2926 ,  Y10T442/2992 ,  Y10T442/3065

Abstract: A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.

Abstract translation: 这里描述了制造电路板的方法。 该方法可以包括添加树脂，形成第一和第二玻璃纤维纤维，以及形成能够传输电信号的第一和第二信号线迹线。 在一些实例中，第一信号线迹线附近的玻璃纤维和树脂材料之间的比率类似于第二信号线迹线附近的玻璃纤维和树脂材料之间的比率。 在一些示例中，第一和第二玻璃纤维光纤在第一和第二信号线迹线附近对角地交叉。 在一些示例中，第一和第二玻璃纤维纤维以锯齿形图案在第一和第二信号线迹线附近交叉。

公开(公告)号：US08493056B2

公开(公告)日：2013-07-23

申请号：US13106720

申请日：2011-05-12

Applicant: Iain Barnett ,  William Michael James Holland ,  Jonathan Ephraim David Hurwitz

Inventor： Iain Barnett ,  William Michael James Holland ,  Jonathan Ephraim David Hurwitz

IPC: G01R19/00

CPC classification number: H05K1/162 ,  G01R15/06 ,  G01R15/16 ,  G01R19/12 ,  G01R19/175 ,  H03H7/004 ,  H05K1/0239 ,  H05K1/0256 ,  H05K2201/09309 ,  H05K2201/09972

Abstract: A voltage measurement circuit is operative to measure a high voltage AC signal and includes a capacitive divider circuit and a compensator circuit. The capacitive divider circuit includes first and second inputs, across which, in use, is received a high voltage AC signal and also includes second and third capacitors. First and second plates of each of the first, second and third capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and third capacitors being defined by a non-conducting part of the printed circuit board. A compensator circuit has a configurable transfer function and includes an input connected across the first and second plates of the third capacitor and an output. The compensator circuit is operative to change a voltage received at its input in accordance with the transfer function and to provide the changed voltage at its output.

Abstract translation: 电压测量电路用于测量高压AC信号，并包括电容分压器电路和补偿电路。 电容分压器电路包括第一和第二输入，在使用中，它们被接收高压AC信号，并且还包括第二和第三电容器。 第一，第二和第三电容器中的每一个的第一和第二板由印刷电路板的导电层限定，并且第一，第二和第三电容器中的每一个的电介质由印刷电路板的非导电部分限定 。 补偿电路具有可配置的传递函数，并且包括连接在第三电容器的第一和第二板上的输入端和输出端。 补偿电路可操作以根据传递函数改变其输入处接收的电压，并在其输出端提供改变的电压。

公开(公告)号：US20130082364A1

公开(公告)日：2013-04-04

申请号：US13250697

申请日：2011-09-30

Applicant: Chuei-Tang Wang ,  Der-Chyang Yeh

Inventor： Chuei-Tang Wang ,  Der-Chyang Yeh

IPC: H01L23/58 ,  H01L21/768

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/64 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81191 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/0715 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract translation: 集成电路结构包括基板，在基板的第一侧上的感光模制件，在模制件中形成的通孔，以及沉积在基板的第一侧和通孔中的一致的金属层。 可以通过在模制件中与通孔对准的基板形成贯通孔，其中导电衬垫沉积在贯通通孔中，以与适形金属层电接触。 集成电路结构还可以包括诸如焊球之间的连接器元件，该连接器元件在通孔的端部上，与第一侧相反的第二面上。 集成电路结构还可以包括在基板的第一侧上的与另一通孔或再分布层电接触的管芯。

公开(公告)号：US08380080B2

公开(公告)日：2013-02-19

申请号：US12554251

申请日：2009-09-04

Applicant: Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga

Inventor： Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga

IPC: H04B10/12 ,  H04B10/00

CPC classification number: H05K1/147 ,  H05K1/0234 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/167 ,  H05K1/189 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/09972 ,  H05K2201/10121

Abstract: An optical transceiver of the present invention comprising an OSA, a circuit board, and a flexible substrate connecting these, in which the flexible substrate has high-speed signal lines and other lines other than the high speed signal lines provided separated from each other on the same surface, a ground layer placed apart and opposite these, and a resistive layer placed apart and opposite the high-speed signal lines, the other lines and the ground layer. High-speed signal and the resistive layer are opposite at least a part of the other lines.

Abstract translation: 本发明的光收发器包括OSA，电路板和连接它们的柔性基板，其中柔性基板具有高速信号线和除了在其上分离的高速信号线之外的其它线 相同的表面，与这些放置分离并相对的接地层，以及与高速信号线，其他线路和接地层分开并相对的电阻层。 高速信号和电阻层与其他线路的至少一部分相对。

公开(公告)号：US20120320559A1

公开(公告)日：2012-12-20

申请号：US13587258

申请日：2012-08-16

Applicant: Jun'ichi KIMURA

Inventor： Jun'ichi KIMURA

IPC: H05K9/00

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/49805 ,  H01L2924/0002 ,  H01L2924/1815 ,  H05K1/0218 ,  H05K3/284 ,  H05K2201/09972 ,  H01L2924/00

Abstract: A module includes a circuit board, a first and a second circuit block mounted on the top surface of the circuit board, and a first boundary formed between these circuit blocks. The module further includes a first metal piece and a resin part. The first metal piece is mounted on the first boundary. The resin part is provided, on its upper surface, with a first groove in a position corresponding to the first metal piece. The first groove includes a first exposed portion in which the first metal piece is partially exposed from the resin part and is connected to a shielded conductor.

Abstract translation: 模块包括电路板，安装在电路板的顶表面上的第一和第二电路块以及在这些电路块之间形成的第一边界。 该模块还包括第一金属片和树脂部。 第一个金属片安装在第一个边界上。 树脂部分在其上表面上设置有与第一金属片对应的位置的第一凹槽。 第一凹槽包括第一暴露部分，其中第一金属片部分地从树脂部分露出并连接到屏蔽导体。