公开(公告)号：US4463059A

公开(公告)日：1984-07-31

申请号：US394014

申请日：1982-06-30

申请人： Somnath Bhattacharya ,  Dudley A. Chance ,  Nicholas G. Koopman ,  Sudipta K. Ray

发明人： Somnath Bhattacharya ,  Dudley A. Chance ,  Nicholas G. Koopman ,  Sudipta K. Ray

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/538 ,  H05K3/24 ,  H05K3/06

CPC分类号： H05K3/244 ,  H01L23/49866 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/388 ,  Y10T428/12507 ,  Y10T428/12528 ,  Y10T428/12583 ,  Y10T428/12882

摘要： The top surface metallurgy of LSI chip carriers is improved by multiple and phased interface of metal layers which enable such metallurgies to be suitable for joining by solder reflow and wire bonding techniques. The modifications result in separating the solder bonding metallurgy from the fan-out conductor metallurgy with an intermediate layer of a metal such as Cr or Ti which prevents the formation of intermetallic alloys which are mechanically weak or brittle and tend to fracture because of thermal fatigue stresses caused by thermal cycling during either multiple (up to 50) solder bonding reflow operations or operation of the circuit. The fan-out metallurgy conductors are preferably composed of Cr-Cu-Cr layers covered by at least one upper metal layer which is separated from the Cu of the conductor by means of a metal such as phased layers of Cr or Ti deposited before the other upper metal layer or layers. Solder ball bonding surfaces are composed of additional metal in the form of Au, Cu and Ni. The solderless bonding surfaces are composed of a metal selected from Au, Cr, Ti, Al and Co.

公开(公告)号：US08466543B2

公开(公告)日：2013-06-18

申请号：US12789316

申请日：2010-05-27

申请人： Thomas J. Fleischman ,  Eric D. Perfecto ,  Sudipta K. Ray

发明人： Thomas J. Fleischman ,  Eric D. Perfecto ,  Sudipta K. Ray

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

摘要： An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.

摘要翻译： 公开了用于连接集成电路器件的装置，系统和方法。 多个初级导电触点和多个初级导电柱电耦合到初级集成电路器件。 多个初级导电触点形成对应于设置在一个或多个次级集成电路器件上的次级导电触点的图案。 多个主导电支柱远离主集成电路装置延伸。 多个主导电柱形成对应于设置在基板上的基板导电触点的图案。 多个初级导电柱和相关联的连接材料提供主集成电路器件和衬底之间的间隔高度，其大于或等于一个或多个次级集成电路器件的高度。

公开(公告)号：US08304290B2

公开(公告)日：2012-11-06

申请号：US12642479

申请日：2009-12-18

申请人： Richard S. Graf ,  Thomas E. Lombardi ,  Sudipta K. Ray ,  David J. West

发明人： Richard S. Graf ,  Thomas E. Lombardi ,  Sudipta K. Ray ,  David J. West

IPC分类号： H01L21/00

CPC分类号： H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/1413 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14179 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/10674 ,  H05K2203/048 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81805

摘要： An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.

摘要翻译： 公开了用于将集成电路器件连接到衬底的装置，系统和方法。 多个标准直径柱和三个或更多个增加直径的柱布置在集成电路装置上。 增加直径的支柱具有大于标准直径柱的直径和类似于标准直径柱的高度。 标准直径柱和增加的直径柱在集成电路器件上形成对应于与集成电路器件相对的衬底上的接触焊盘的图案。 第一组焊料凸点设置在标准直径柱和接触垫之间。 第二组焊料凸点设置在增加直径的支柱和接触垫之间。 第二组焊料凸块的预连接高度大于第一组焊料凸点的预连接高度。

公开(公告)号：US07281667B2

公开(公告)日：2007-10-16

申请号：US10907761

申请日：2005-04-14

申请人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

发明人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC分类号： G06K19/06

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US06574859B2

公开(公告)日：2003-06-10

申请号：US09785787

申请日：2001-02-16

申请人： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

发明人： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC分类号： H05K336

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

摘要： An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

摘要翻译： 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在后续参考低温期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。在第一种方法中，通过掩模掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。在第二种方法中，将瞬态熔融焊膏的组成中的焊料预成型件润湿到电子模块I / O焊盘上，然后连接互连柱或焊球。连接电子 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行电路卡的模块。

公开(公告)号：US06335210B1

公开(公告)日：2002-01-01

申请号：US09466607

申请日：1999-12-17

申请人： Mukta S. Farooq ,  Raymond A. Jackson ,  Sarah H. Knickerbocker ,  Sudipta K. Ray

发明人： Mukta S. Farooq ,  Raymond A. Jackson ,  Sarah H. Knickerbocker ,  Sudipta K. Ray

IPC分类号： H01L2166

CPC分类号： G01R31/2863 ,  H01L2224/16225 ,  H01L2924/15311

摘要： The present invention relates generally to a new structure and method for chip burn-in and/or testing. More particularly, the invention encompasses a baseplate that is secured to a delicate chip and a method for such an invention is also disclosed. The inventive baseplate provides an added strength to a complex chip while it is being tested and/or burned-in, and then during normal use the baseplate of this invention is an integrated component of the chip.

摘要翻译： 本发明一般涉及用于芯片老化和/或测试的新结构和方法。 更具体地，本发明包括固定到精细芯片上的底板，并且还公开了用于这种发明的方法。 本发明的基板在被测试和/或燃烧时提供了对复合芯片的附加强度，然后在正常使用期间，本发明的底板是芯片的集成部件。

公开(公告)号：US06270363B1

公开(公告)日：2001-08-07

申请号：US09315373

申请日：1999-05-18

申请人： Peter J. Brofman ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

发明人： Peter J. Brofman ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC分类号： H01R458

CPC分类号： H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/293 ,  H01L2224/81101 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01R12/52 ,  H01R13/2414 ,  H01R43/0256 ,  H05K3/321 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0162 ,  H05K2201/0272 ,  H05K2201/0284 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0425 ,  H01L2924/00 ,  H01L2224/05599

摘要： A compressible interposer comprising an interposer sheet having a plurality of apertures filled with a dielectric material having a substantially uniform suspension of conductive particles therein forming a plurality of conductive sites. Preferably, the number of conductive sites on the interposer are greater in number than the number of contact pads on the electronic components such that precise alignment of the interposer between the electronic components is not required. The apertures of the interposer sheet confine the conductive particles within the dielectric material such that during compression of the interposer between the electronic components, z-axis conductive pathways are formed without shorting in the x and y directions. Preferably, the interposer sheet comprises polyimide. Preferably, the dielectric material comprises polyimide-siloxane. Preferably, the conductive particles have a diameter of about 2 to about 20 &mgr;m and comprise of a material selected from the group consisting of copper, gold, silver, nickel, palladium, platinum, and alloys thereof. The particles may also be coated with an additional conductive material such as solder having a lower melting temperature. Most preferably, the conductive particles comprise solder coated copper particles. The conductive particles are present in an amount of about 30 to about 90 wt. % of the total weight of the conductive particles and the dielectric material.

摘要翻译： 一种可压缩插入件，其包括插入片，所述插入片具有填充有形成多个导电部位的导电粒子的基本均匀悬浮液的电介质材料的多个孔。 优选地，内插器上的导电位置的数量大于电子部件上的接触焊盘的数量，使得不需要电子部件之间的插入器的精确对准。 插入片的孔径将导电粒子限制在电介质材料内，使得在电子部件之间的插入件压缩期间，在x和y方向上形成z轴传导路径而不会短路。 优选地，插入片包括聚酰亚胺。 优选地，电介质材料包括聚酰亚胺 - 硅氧烷。 优选地，导电颗粒的直径为约2至约20μm，并且包括选自铜，金，银，镍，钯，铂及其合金的材料。 颗粒也可以涂覆有另外的导电材料，例如具有较低熔融温度的焊料。 最优选地，导电颗粒包括焊料涂覆的铜颗粒。 导电颗粒的存在量为约30至约90wt。 导电颗粒和电介质材料的总重量的百分比。

公开(公告)号：US5961032A

公开(公告)日：1999-10-05

申请号：US884977

申请日：1997-06-30

申请人： James H. Covell, II ,  Shaji Farooq ,  Peter A. Gruber ,  Sudipta K. Ray

发明人： James H. Covell, II ,  Shaji Farooq ,  Peter A. Gruber ,  Sudipta K. Ray

IPC分类号： B22C9/22 ,  B23K3/06 ,  B23K35/02 ,  H01L21/60 ,  H01L23/12 ,  H01L23/50 ,  H05K3/34 ,  B23K35/012 ,  B23K31/002 ,  B22C9/020

CPC分类号： H05K3/3468 ,  B22C9/22 ,  B23K3/0607 ,  B23K35/0222 ,  B23K2201/40 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K3/3463

摘要： A method is described for forming solder mounds for attachment to electronic devices. The solder mounds are preferably in the form of columns and comprise a first solder portion and a second solder portion with the two solder portions having different melting points. The solder columns are preferably formed using an injection molding device. The method is directed to the use of a single column mold to form the multi-solder column. In one embodiment, deformable material is used to partially block a portion of the through opening of the mold during a first solder injection process. The deformable material is then removed and the remainder of the through openings of the mold filled with a second molten solder. The multi-solder column is then electrically connected to a substrate by reflowing.

摘要翻译： 描述了用于形成用于附接到电子设备的焊接凸块的方法。 焊料块优选为柱状，并且包括第一焊料部分和第二焊料部分，其中两个焊料部分具有不同的熔点。 焊料柱优选使用注射成型装置形成。 该方法涉及使用单柱模具来形成多焊料柱。 在一个实施例中，可变形材料用于在第一次焊接注入过程期间部分地阻挡模具的通孔的一部分。 然后去除可变形材料，并且模具的通孔的其余部分填充有第二熔融焊料。 然后通过回流将多焊料柱电连接到衬底。

公开(公告)号：US5436412A

公开(公告)日：1995-07-25

申请号：US102027

申请日：1993-08-03

申请人： Umar M. U. Ahmad ,  Ananda H. Kumar ,  Eric D. Perfecto ,  Chandrika Prasad ,  Sampath Purushothaman ,  Sudipta K. Ray

发明人： Umar M. U. Ahmad ,  Ananda H. Kumar ,  Eric D. Perfecto ,  Chandrika Prasad ,  Sampath Purushothaman ,  Sudipta K. Ray

IPC分类号： H01L23/12 ,  H01L23/32 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K1/02

CPC分类号： H05K1/113 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/48463 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K3/0041 ,  H05K3/4076 ,  H05K3/4605 ,  H05K3/467

摘要： An electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electrically connected to the capture pad. The bonding pad and the second layer of polymeric material are at the same height so that the bonding pad is level with the second layer of polymeric material. Finally, there is a cap of electrically conducting metallization on the bonding pad and extending beyond the second layer of polymeric material. The cap is of a different composition than the bonding pad.

摘要翻译： 一种用于将衬底连接到下一级封装或半导体器件的电互连结构。 所述互连结构包括至少两层聚合材料，所述层中的一个具有捕获垫，并且所述层中的第二层具有电连接到所述捕获垫的接合焊盘。 接合焊盘和第二层聚合物材料处于相同的高度，使得焊盘与第二层聚合物材料平齐。 最后，在焊盘上存在导电金属化的帽，并延伸超过第二层聚合物材料。 盖子具有与接合垫不同的成分。

公开(公告)号：US5209817A

公开(公告)日：1993-05-11

申请号：US748445

申请日：1991-08-22

申请人： Umar M. Ahmad ,  Daniel G. Berger ,  Ananda Kumar ,  Susan J. LaMaire ,  Keshav B. Prasad ,  Sudipta K. Ray ,  Kwong H. Wong

发明人： Umar M. Ahmad ,  Daniel G. Berger ,  Ananda Kumar ,  Susan J. LaMaire ,  Keshav B. Prasad ,  Sudipta K. Ray ,  Kwong H. Wong

IPC分类号： H01L23/498 ,  H01L23/522 ,  H05K1/03 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46

CPC分类号： H05K3/4644 ,  H01L23/49827 ,  H01L23/5226 ,  H05K3/4605 ,  H05K3/465 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2203/0597 ,  H05K2203/072 ,  H05K3/0023 ,  H05K3/061 ,  H05K3/108 ,  H05K3/184 ,  H05K3/388 ,  H05K3/4661

摘要： In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

摘要翻译： 在多层布线结构中，通过诸如铜之类的导电材料的各向同性的沉积，形成导线和通孔，在诸如聚酰亚胺的电介质基底上。 在本发明的一个优选实施例中，将铜电镀到沉积在已经形成通孔开口的电介质基底的表面上的薄种子传导层。 在种子层上形成在电介质基底表面上的抗蚀剂中的开口形成限定布线和通孔导体特征的图案。 电镀铜在各向同性地填充抗蚀剂中的通孔开口和线图案开口，使得当电镀步骤完成时，布线和通孔的上表面是共面的。 在添加其后的布线层次时，去除抗蚀剂，并且通孔导体和布线图案被另一个介电层覆盖，该介质层既封装了前一层的导体并用作下一层的基底，其形成方式与前述 水平。