Patent search ap:("INFINEON TECHNOLOGIES AG") AND inv:"Georg Meyer-Berg" Page 2

11.

发明授权
Chip package and a wafer level package 有权

公开(公告)号：US10522447B2

公开(公告)日：2019-12-31

申请号：US15883151

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H01L23/34 , H01L23/495 , H01L21/56 , H01L23/00 , H01L21/48 , H01L25/065 , H01L23/31

Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

12.

发明申请
Metallic Interconnect, a Method of Manufacturing a Metallic Interconnect, a Semiconductor Arrangement and a Method of Manufacturing a Semiconductor Arrangement 审中-公开

公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel , Khalil Hosseini , Johannes Lodermeyer , Joachim Mahler , Thorsten Meyer , Georg Meyer-Berg , Ivan Nikitin , Reinhard Pufall , Edmund Riedl , Klaus Schmidt , Manfred Schneegans , Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

13.

发明授权
Method of manufacturing a semiconductor component and semiconductor component 有权

公开(公告)号：US10121690B2

公开(公告)日：2018-11-06

申请号：US14757589

申请日：2015-12-23

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg , Edward Fuergut , Joachim Mahler

IPC: H01L21/00 , H01L21/683 , H01L23/00 , H01L21/56 , H01L23/31

Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.

14.

发明授权
Semiconductor package with interlocked connection 有权

公开(公告)号：US10090216B2

公开(公告)日：2018-10-02

申请号：US15442084

申请日：2017-02-24

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg , Reinhard Pufall , Michael Goroll , Rainer Dudek

IPC: H01L23/04 , H05K1/18 , H01L25/10

Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.

15.

发明授权
Chip package and a wafer level package 有权

公开(公告)号：US09917036B2

公开(公告)日：2018-03-13

申请号：US14827361

申请日：2015-08-17

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H01L23/043 , H01L23/495 , H01L21/56 , H01L23/00 , H01L21/48 , H01L25/065 , H01L23/31

CPC classification number: H01L23/49513 , H01L21/4821 , H01L21/561 , H01L23/3128 , H01L23/49541 , H01L23/49575 , H01L23/49582 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/32 , H01L24/82 , H01L25/0655 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/24155 , H01L2224/29082 , H01L2224/29139 , H01L2224/29144 , H01L2224/29155 , H01L2224/29164 , H01L2224/2919 , H01L2224/32245 , H01L2224/73267 , H01L2224/82007 , H01L2924/01028 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/06 , H01L2924/0665 , H01L2924/07025 , H01L2924/07802 , H01L2924/12042 , H01L2924/1715 , H01L2924/17738 , H01L2924/17747 , H01L2924/1776 , H01L2924/17763 , H01L2924/181 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/20643 , H01L2924/20644 , H01L2924/20645 , H01L2924/20646 , H01L2924/20647 , H01L2924/20648 , H01L2924/20649 , H01L2924/2065 , H01L2924/00

Abstract: Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

16.

发明申请
SEMICONDUCTOR DEVICE INCLUDING AN ANTENNA 审中-公开

公开(公告)号：US20170236776A1

公开(公告)日：2017-08-17

申请号：US15045687

申请日：2016-02-17

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh , Franz-Xaver Muehlbauer , Claus Waechter , Veronika Huber , Dominic Maier , Thomas Kilger , Saverio Trotta , Ashutosh Baheti , Georg Meyer-Berg , Maciej Wojnowski

IPC: H01L23/498 , H01L23/367 , H01L21/56 , H01L23/31

CPC classification number: H01L23/49822 , H01L21/56 , H01L23/3114 , H01L23/3672 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L2223/6677 , H01L2223/6683 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267 , H01L2924/18162 , H01Q1/2283 , H01Q9/0407 , H01Q9/265 , H01Q9/285 , H01Q21/061 , H01Q21/065

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

17.

发明申请
Method of manufacturing a semiconductor component and semiconductor component 审中-公开
Title translation: 制造半导体部件和半导体部件的方法

公开(公告)号：US20160181138A1

公开(公告)日：2016-06-23

申请号：US14757589

申请日：2015-12-23

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg , Edward Fuergut , Joachim Mahler

IPC: H01L21/683 , H01L21/768 , H01L21/56 , H01L23/528 , H01L21/78

CPC classification number: H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/94 , H01L24/96 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/04105 , H01L2224/06181 , H01L2224/2518 , H01L2224/32225 , H01L2224/94 , H01L2224/83

Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.

Abstract translation: 各种实施例提供制造半导体部件的方法，其中所述方法包括提供包括载体的层堆叠和在一侧上包括金属化层的薄化晶片，其中所述薄化晶片被放置在所述载体的第一侧上; 至少部分地形成封装所述层堆叠的封装; 随后从所述载体的第二侧使所述载体变薄，其中所述第二侧与所述载体的第一侧相对。

18.

发明授权
Electronic component with sheet-like redistribution structure 有权

公开(公告)号：US09349709B2

公开(公告)日：2016-05-24

申请号：US14096063

申请日：2013-12-04

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl , Georg Meyer-Berg

IPC: H01L23/04 , H01L25/065 , H01L25/00 , H01L23/00 , H01L21/78 , H01L23/373 , H01L23/492 , H01L23/498 , H01L25/10 , H01L23/31

CPC classification number: H01L25/0655 , H01L21/78 , H01L23/3121 , H01L23/3735 , H01L23/492 , H01L23/49811 , H01L23/49816 , H01L23/49844 , H01L24/03 , H01L24/06 , H01L24/36 , H01L24/37 , H01L24/40 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/02371 , H01L2224/04042 , H01L2224/05024 , H01L2224/37147 , H01L2224/40137 , H01L2224/40139 , H01L2224/40225 , H01L2224/48091 , H01L2224/48137 , H01L2224/83801 , H01L2224/8384 , H01L2224/84801 , H01L2224/8484 , H01L2924/00014 , H01L2924/01029 , H01L2924/07025 , H01L2924/1203 , H01L2924/12042 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

Abstract: An electronic component comprising an electrically conductive chip carrier comprising an electrically insulating core structure at least partially covered with electrically conductive material, at least one electronic chip each having a first main surface attached to the chip carrier, and a sheet-like redistribution structure attached to a second main surface of the at least one electronic chip and configured for electrically connecting the second main surface of the at least one electronic chip with the chip carrier.

19.

发明申请
Power Semiconductor Module Having a Direct Copper Bonded Substrate and an Integrated Passive Component, and an Integrated Power Module 审中-公开
Title translation: 具有直接铜键合基板和集成无源元件的功率半导体模块以及集成功率模块

公开(公告)号：US20160126192A1

公开(公告)日：2016-05-05

申请号：US14529371

申请日：2014-10-31

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld , Juergen Hoegerl , Gottfried Beer , Magdalena Hoier , Georg Meyer-Berg

IPC: H01L23/538 , H01L21/48 , H01L21/56

CPC classification number: H01L23/5389 , H01L21/486 , H01L21/561 , H01L23/3135 , H01L23/3735 , H01L23/49811 , H01L23/5384 , H01L23/5386 , H01L24/00 , H01L25/00

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract translation: 功率半导体模块包括具有陶瓷衬底的直接铜键合（DCB）衬底，与陶瓷衬底的第一主表面接合的第一铜金属化层和与陶瓷衬底的第一主表面相对的陶瓷衬底的第二主表面接合的第二铜金属化主表面。功率半导体模块还包括附接第一铜金属化的功率半导体管芯，连接第一铜金属化的无源部件，封装功率半导体管芯和无源部件的第一隔离层，第一隔离层上的第一结构化金属化层，以及从第一结构化金属化层延伸穿过第一隔离层到功率半导体管芯和无源部件的第一多个导电通孔。还提供了集成电源模块和制造集成电源模块的方法。