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    ELECTRONIC DEVICE PACKAGE WITH REDUCED THICKNESS VARIATION
    11.
    发明申请
    ELECTRONIC DEVICE PACKAGE WITH REDUCED THICKNESS VARIATION 审中-公开

    公开(公告)号：US20200312787A1

    公开(公告)日：2020-10-01

    申请号：US16369681

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Yonggang Li ,  Brandon C. Marin ,  Vahidreza Parichehreh ,  Jeremy D. Ecton

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48

    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.

    LASER PLANARIZATION WITH IN-SITU SURFACE TOPOGRAPHY CONTROL AND METHOD OF PLANARIZATION
    12.
    发明申请
    LASER PLANARIZATION WITH IN-SITU SURFACE TOPOGRAPHY CONTROL AND METHOD OF PLANARIZATION 审中-公开

    公开(公告)号：US20200078884A1

    公开(公告)日：2020-03-12

    申请号：US16124292

    申请日：2018-09-07

    Applicant: Intel Corporation

    Inventor： Bai Nie ,  Yonggang Li

    IPC: B23K26/352 ,  H05K3/00 ,  C23C14/02 ,  C23C18/18

    Abstract: A system and method of planarizing a layer are disclosed. Topography of the layer is measured to produce a topographic map, which is then digitized into blocks of that indicate different thickness variation. Laser conditions are assigned for each block, a laser steered to planarization blocks where material is to be removed, and the material ablated at each planarization block. In-situ monitoring of the surface profile provides feedback to adjust the laser conditions during planarization. When depth control is used, the laser is focused at a focal plane and has a focal depth beyond which no material is ablated and the laser is steered across the entire layer. A thin metal layer of higher ablation threshold than the dielectric layer formed over the layer provides added selectivity, with the laser conditions changed after ablation of the metal layer. Otherwise, planarization is limited to the planarization blocks.

    Hybrid core through holes and vias
    17.
    发明授权
    Hybrid core through holes and vias 有权
    混合核心通孔和通孔

    公开(公告)号：US08928151B2

    公开(公告)日：2015-01-06

    申请号：US14019759

    申请日：2013-09-06

    Applicant: Intel Corporation

    Inventor： Mihir K. Roy ,  Islam Salama ,  Yonggang Li

    IPC: H01L23/48 ,  H01L23/498

    CPC classification number: H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

    Abstract translation: 半导体器件基板包括前部和后部，其是设置在第一芯的前表面和后表面上的层叠芯。 第一芯具有圆柱形电镀通孔，其已被金属电镀并填充有空芯材料。 前部和后部具有激光钻孔的锥形通孔，其填充有导电材料并且连接到电镀通孔。 后部包括与前部连通的整体电感线圈。 第一芯和层叠芯形成具有集成电感线圈的混合芯半导体器件衬底。

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