公开(公告)号：US10103094B2

公开(公告)日：2018-10-16

申请号：US15626687

申请日：2017-06-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H05K1/00 ,  H01L23/498 ,  H01L23/48 ,  H01L23/36 ,  H01L23/373 ,  H01L21/768 ,  H01L23/367

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

公开(公告)号：US09876002B2

公开(公告)日：2018-01-23

申请号：US15419237

申请日：2017-01-30

Applicant: Invensas Corporation

Inventor： Terrence Caskey ,  Ilyas Mohammed

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/13 ,  H01L23/538 ,  H01L25/11 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/852 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

公开(公告)号：US09379008B2

公开(公告)日：2016-06-28

申请号：US14627252

申请日：2015-02-20

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Terrence Caskey

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L21/3205 ,  H01L23/14 ,  H01L23/525

CPC classification number: H01L21/76877 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/525 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

公开(公告)号：US20160035712A1

公开(公告)日：2016-02-04

申请号：US14883977

申请日：2015-10-15

Applicant: Invensas Corporation

Inventor： Terrence Caskey ,  Ilyas Mohammed

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/852 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

公开(公告)号：US09064933B2

公开(公告)日：2015-06-23

申请号：US13724223

申请日：2012-12-21

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Michael Newman ,  Charles G. Woychik ,  Terrence Caskey

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/78 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract translation: 本文公开了形成微电子组件的方法以及所得到的结构和装置。 在一个实施例中，形成微电子组件的方法包括去除在衬底的表面的部分处暴露的材料，以形成经处理的衬底，该衬底具有多个由处理衬底的整体支撑部分分隔开的薄化部分，该部分的厚度大于厚度 减薄部分中的至少一些薄化部分包括在薄壁部分的厚度方向上延伸并在表面露出的多个导电互连件; 以及去除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的变薄部分，包括互连。

公开(公告)号：US20150034371A1

公开(公告)日：2015-02-05

申请号：US14517268

申请日：2014-10-17

Applicant: INVENSAS CORPORATION

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Terrence Caskey ,  Reynaldo Co ,  Ellis Chau

IPC: H05K1/18

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Abstract translation: 结构可以包括在第一表面的第一部分和远离基底的端表面处具有连接到导电元件的基底的结合元件。 电介质封装元件可以从第一部分覆盖并延伸并填充接合元件之间的空间，以将接合元件彼此分开。 封装元件具有背离第一表面的第三表面。 粘合元件的未封装部分由在第三表面处被封装元件未覆盖的至少部分端面限定。 封装元件至少部分地限定除了第一部分之外的第一表面的第二部分，并且具有尺寸适于容纳微电子元件的整个区域的区域。 一些导电元件位于第二部分并被配置为与这种微电子元件连接。

公开(公告)号：US20140175671A1

公开(公告)日：2014-06-26

申请号：US13722189

申请日：2012-12-20

Applicant: INVENSAS CORPORATION

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Terrence Caskey ,  Reynaldo Co ,  Ellis Chau

IPC: H01L23/528 ,  H01L23/00 ,  H05K1/18

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Abstract translation: 结构可以包括在第一表面的第一部分和远离基底的端表面处具有连接到导电元件的基底的结合元件。 电介质封装元件可以从第一部分覆盖并延伸并填充接合元件之间的空间，以将接合元件彼此分开。 封装元件具有背离第一表面的第三表面。 粘合元件的未封装部分由在第三表面处被封装元件未覆盖的至少部分端面限定。 封装元件至少部分地限定除了第一部分之外的第一表面的第二部分，并且具有尺寸适于容纳微电子元件的整个区域的区域。 一些导电元件位于第二部分并被配置为与这种微电子元件连接。

公开(公告)号：US20150340310A1

公开(公告)日：2015-11-26

申请号：US14815282

申请日：2015-07-31

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

Abstract translation: 互连元件包括具有第一厚度并限定第一表面的半导体或绝缘材料层; 导热层; 多个导电元件; 和介电涂层。 导热层包括至少10微米的第二厚度并且限定互连元件的第二表面。 多个导电元件从互连元件的第一表面延伸到互连元件的第二表面。 电介质涂层位于每个导电元件的至少一部分和导热层之间。

公开(公告)号：US20150255345A1

公开(公告)日：2015-09-10

申请号：US14722672

申请日：2015-05-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Michael Newman ,  Charles G. Woychik ,  Terrence Caskey

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract translation: 本文公开了形成微电子组件的方法以及所得到的结构和装置。 在一个实施例中，形成微电子组件的方法包括去除在衬底的表面的部分处暴露的材料，以形成经处理的衬底，该衬底具有多个由处理衬底的整体支撑部分分离的薄化部分，该部分厚度大于厚度 减薄部分中的至少一些薄化部分包括在薄壁部分的厚度方向上延伸并在表面露出的多个导电互连件; 以及去除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的变薄部分，包括互连。

公开(公告)号：US09000600B2

公开(公告)日：2015-04-07

申请号：US14204860

申请日：2014-03-11

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Kishor V. Desai ,  Huailiang Wei ,  Craig Mitchell ,  Belgacem Haba

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L23/34 ,  H01L21/76841 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/32105 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81805

Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.

Abstract translation: 部件可以包括在基板的开口内延伸的基板和导电通孔。 基底可以具有第一和第二相对表面。 开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。 电介质材料可以在内壁暴露。 导电通孔可以在邻近第一表面的开口内限定释放通道。 释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度 在飞机上开了 边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。