公开(公告)号：US08895368B2

公开(公告)日：2014-11-25

申请号：US14133593

申请日：2013-12-18

申请人： ChipMOS Technologies Inc.

发明人： Chien-Hao Wang

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L21/568 ,  H01L24/03 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2924/014

摘要： A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals.

摘要翻译： 制造芯片封装结构的方法包括以下步骤。 提供具有金属层的载体。 在金属层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层具有暴露金属层的一部分的多个第一开口。 连接端子分别形成在第一开口中，并且连接端子连接到金属层。 将芯片放置在载体上，并且芯片的第一焊盘通过多个连接导体分别连接到连接端子。 将芯片放置在载体上之后，去除图案化的光致抗蚀剂层。 在载体上形成密封剂。 密封剂封装芯片，连接导体和金属层。 移除载体和金属层以露出连接端子。

公开(公告)号：US08877630B1

公开(公告)日：2014-11-04

申请号：US14078240

申请日：2013-11-12

申请人： ChipMos Technologies Inc.

发明人： Shih Jye Cheng ,  Tung Bao Lu

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L21/4853 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05027 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/8159 ,  H01L2224/8169 ,  H01L2224/81744 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81862 ,  H01L2224/83104 ,  H01L2924/01322 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/1182 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/1146

摘要： The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a conductive pad on a semiconductor die; forming a seed layer over the conductive pad; defining a first mask layer over the seed layer; and forming a silver alloy bump body in the first mask layer. The forming a silver alloy bump body in the first mask layer includes operations of preparing a first cyanide-based bath; controlling a pH value of the first cyanide-based bath to be within a range of from about 6 to about 8; immersing the semiconductor die into the first cyanide-based bath; and applying an electroplating current density of from about 0.1 ASD to about 0.5 ASD to the semiconductor die.

摘要翻译： 本公开提供了一种用于制造半导体结构的方法。 该方法包括在半导体管芯上形成导电焊盘; 在所述导电垫上形成种子层; 限定种子层上的第一掩模层; 以及在所述第一掩模层中形成银合金凸块体。 在第一掩模层中形成银合金凸块体包括制备第一氰化物基浴的操作; 将第一氰化物基浴的pH值控制在约6至约8的范围内; 将半导体管芯浸入第一氰化物浴中; 以及向半导体管芯施加约0.1ASD至约0.5ASD的电镀电流密度。

公开(公告)号：US20140322869A1

公开(公告)日：2014-10-30

申请号：US14133593

申请日：2013-12-18

申请人： ChipMOS Technologies Inc.

发明人： Chien-Hao Wang

IPC分类号： H01L21/56 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L21/568 ,  H01L24/03 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2924/014

摘要： A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals.

摘要翻译： 制造芯片封装结构的方法包括以下步骤。 提供具有金属层的载体。 在金属层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层具有暴露金属层的一部分的多个第一开口。 连接端子分别形成在第一开口中，并且连接端子连接到金属层。 将芯片放置在载体上，并且芯片的第一焊盘通过多个连接导体分别连接到连接端子。 将芯片放置在载体上之后，去除图案化的光致抗蚀剂层。 在载体上形成密封剂。 密封剂封装芯片，连接导体和金属层。 移除载体和金属层以露出连接端子。

公开(公告)号：US08836144B2

公开(公告)日：2014-09-16

申请号：US13846608

申请日：2013-03-18

申请人： Chipmos Technologies Inc.

发明人： Tsung Jen Liao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73277 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

摘要翻译： 本发明提供一种半导体封装结构，其包括管芯，多个接合线，密封剂和多个第一外部端子。 模具具有活性表面和背面。 每个接合线的第一端连接到管芯的后表面，并且与第一端相对的第二端电连接到管芯的有效表面。 密封剂覆盖管芯的背面和接合线，其中每个接合线的一部分从密封剂露出。 第一外部端子设置在密封剂的顶表面上，并且分别覆盖接合线的暴露部分并且电连接到接合线。

公开(公告)号：US08723316B2

公开(公告)日：2014-05-13

申请号：US13481881

申请日：2012-05-28

申请人： Wei-Ming Chen ,  Chi-Chia Huang

发明人： Wei-Ming Chen ,  Chi-Chia Huang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/4985 ,  H01L21/563 ,  H01L23/49894 ,  H01L23/552 ,  H01L23/60 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate.

摘要翻译： 芯片封装结构包括具有芯片安装区域的柔性衬底，设置在柔性衬底上的多个引线，绝缘层和芯片。 每个引线包括彼此连接的主体部分和内部引线部分。 主体部分位于芯片安装区域的外侧，其厚度大于内部引线部分的厚度。 绝缘层设置在内引线部分上。 芯片具有活性表面，多个凸起和与芯片边缘相邻的密封环设置在该表面上。 芯片安装在芯片安装区域内，通过将引线的内引线部分与凸块连接来电连接柔性基板。 当芯片电连接到柔性基板时，绝缘层对应于密封环就位。

公开(公告)号：US08712932B2

公开(公告)日：2014-04-29

申请号：US13543421

申请日：2012-07-06

申请人： Geng-Shin Shen ,  Hui-Chung Che

发明人： Geng-Shin Shen ,  Hui-Chung Che

IPC分类号： G06F15/18

CPC分类号： G06Q50/184 ,  G06F2216/11

摘要： A computer implemented apparatus for automatically generating and filtering creative proposals is disclosed. Particularly, the computer implemented apparatus automatically generates all possible featured component code sets which corresponding to all possible featured components, and compares them to the prior art code sets which corresponding to the prior objects. Thereby, the novel code sets which corresponding to the novel creative proposals are rapidly filtered out. The computer implemented apparatus comprises a standard component database, a permutation and combination module, a featured component code set database, a prior art code set database, a matching module, a sifting module and an output module.

摘要翻译： 公开了一种用于自动生成和过滤创意提案的计算机实现的装置。 特别地，计算机实现的装置自动生成对应于所有可能的特征分量的所有可能的特征分量代码集，并将它们与对应于现有对象的现有技术代码集进行比较。 因此，与新颖的创意提案相对应的新颖代码集被快速过滤掉。 计算机实现的装置包括标准组件数据库，置换和组合模块，特征组件代码集数据库，现有技术代码集数据库，匹配模块，筛选模块和输出模块。

公开(公告)号：US20140061899A1

公开(公告)日：2014-03-06

申请号：US13846608

申请日：2013-03-18

申请人： CHIPMOS TECHNOLOGIES INC

发明人： TSUNG JEN LIAO

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73277 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

摘要翻译： 本发明提供一种半导体封装结构，其包括管芯，多个接合线，密封剂和多个第一外部端子。 模具具有活性表面和背面。 每个接合线的第一端连接到管芯的后表面，并且与第一端相对的第二端电连接到管芯的有效表面。 密封剂覆盖管芯的背面和接合线，其中每个接合线的一部分从密封剂露出。 第一外部端子设置在密封剂的顶表面上，并且分别覆盖接合线的暴露部分并且电连接到接合线。

公开(公告)号：US08652882B2

公开(公告)日：2014-02-18

申请号：US13166998

申请日：2011-06-23

申请人： Yu Tang Pan ,  Shih Wen Chou

发明人： Yu Tang Pan ,  Shih Wen Chou

IPC分类号： H01L23/44 ,  H01L23/48

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening.

摘要翻译： 芯片封装方法包括以下步骤：将第一带附接到金属板; 图案化金属板以形成多个端子焊盘和多个引线，其中多个端子焊盘和多个引线设置在中心空隙区域的两个相对侧上，每个侧面上的多个端子焊盘被布置 在离开中心空隙区域的方向上彼此隔开的至少两排，并且每个引线具有延伸到中心空隙区域的第一端部和连接到相应的端子焊盘的第二端部; 将具有开口的第二带附接到所述多个端子焊盘，其中每个所述开口暴露所述引线的中心空隙区域和所述第一端部; 去除第一个磁带; 将芯片附接到所述多个端子焊盘和所述多个引线，其中所述芯片上的多个接合焊盘对应于所述中心空隙区域; 以及通过所述开口将所述接合焊盘连接到所述引线的所述第一端部的多个接合线。

公开(公告)号：US20120241935A1

公开(公告)日：2012-09-27

申请号：US13205649

申请日：2011-08-09

申请人： Shih-Wen Chou ,  Yu-Tang Pan

发明人： Shih-Wen Chou ,  Yu-Tang Pan

IPC分类号： H01L23/34

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package-on-package structure includes first and second package structures and bumps. The first package structure includes a carrier, a chip configured on the carrier, a heat spreader, and an encapsulant. The chip is electrically connected to the carrier through conductive wires. The heat spreader includes a support portion located on the chip and connection portions located respectively at two opposite sides of the support portion. The heat spreader has a circuit layer thereon, covers the chip and the conductive wires, and electrically connects the carrier through the circuit layer on the connecting portions. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader, and a portion of the carrier. The bumps are configured on the support portion. The second package structure is configured on the first package structure and is electrically connected to the first package structure through the bumps.

摘要翻译： 包装封装结构包括第一和第二封装结构和凸块。 第一封装结构包括载体，配置在载体上的芯片，散热器和密封剂。 芯片通过导线与载体电连接。 散热器包括位于芯片上的支撑部分和分别位于支撑部分的相对两侧的连接部分。 散热器在其上具有电路层，覆盖芯片和导线，并且通过连接部分上的电路层将载体电连接。 密封剂封装芯片，导线，散热器的一部分和载体的一部分。 凸起构造在支撑部分上。 第二封装结构被配置在第一封装结构上，并且通过凸块与第一封装结构电连接。

公开(公告)号：US20120153460A1

公开(公告)日：2012-06-21

申请号：US13225488

申请日：2011-09-05

申请人： Chung-Pang Chi

发明人： Chung-Pang Chi

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05547 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A manufacturing method of a bump structure is provided. A substrate having at least one pad and a passivation layer is provided. The passivation layer has at least one first opening exposing the pad. An insulating layer is formed on the passivation layer. The insulating layer has at least one second opening located above the first opening. A metal layer is formed on the insulating layer. The metal layer electrically connects the pad through the first and second openings. A first bump is formed in the first and second openings. A second bump is formed on the first bump and a portion of the metal layer. The metal layer not covered by the second bump is partially removed by using the second bump as a mask, so as to form at least one UBM layer. The first bump is completely covered by the UBM layer and the second bump.

摘要翻译： 提供一种凸块结构的制造方法。 提供具有至少一个焊盘和钝化层的衬底。 钝化层具有至少一个露出该垫的第一开口。 在钝化层上形成绝缘层。 绝缘层具有位于第一开口上方的至少一个第二开口。 在绝缘层上形成金属层。 金属层通过第一和第二开口将焊盘电连接。 在第一和第二开口中形成第一凸块。 在第一凸块和金属层的一部分上形成第二凸块。 通过使用第二凸块作为掩模，部分地除去未被第二凸起覆盖的金属层，以形成至少一个UBM层。 第一个凸块被UBM层和第二个凸块完全覆盖。