Abstract:
The principles described herein relate to methods for soldering electrode terminals, pins or lead-frames of commercial electric components for high temperature reliability. In one embodiment, prior to soldering the electric components, a pre-plated solder layer is removed from the lead frame or pins, and nickel and/or gold films are formed with electroless plating. The removal of the pre-plated solder layer avoids excess pre-plated Sn with high-Pb solder that lowers the melting point to between 180° C. and 220° C. and weakens solder joints. The nickel layer formed with an electroless plating acts as a barrier to the interdiffusion of tin from solder with copper of the lead frame material, which may otherwise occur at high temperatures. Interdiffusion forms an intermetallic compound layer of copper and tin and degrades solder joint strength. The novel soldering processes improve high temperature reliability of solder joints and extend electronics life-time.
Abstract:
A fuse is provided in a circuit, such that the fuse and an electric device in the circuit are thermally coupled to one another. The generation of the amount of heat by the electric device causes a fusible material in the fuse to melt. In this manner, the current terminal path of the electric device is interrupted.
Abstract:
In a soldering method for soldering an electronic component including a palladium or palladium alloy layer formed on a surface of the electronic component and also including a soldering lead terminal onto a printed wiring board including a soldering land and plated through hole, a solder layer containing tin and zinc as main components is formed on the surfaces of the land through hole by a HAL treatment. The lead terminal is inserted and mounted in the through hole. The printed wiring board is brought into contact with jet flows of a solder containing tin and zinc as the main components to thereby supply a solder to the land and through hole.
Abstract:
This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein a joint surface to the package board and an end surface orthogonal to the joint surface are formed on the end of the lead farther from the semiconductor chip, and a metal plating layer made of a pure metal is formed on the end surface.
Abstract:
In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.
Abstract:
A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead frame unit in a stacked semiconductor package may include a die pad supporting a semiconductor chip, an inner lead electrically connected to the semiconductor chip, an outer lead extending from the inner lead, and a heat-resistant insulation member surrounding the connection portion. The outer lead may include a connection portion connected to the inner lead and a junction portion connected to the connection portion and a circuit board. An external signal may be applied to the junction portion. If the lead frame unit is used in the stacked semiconductor package, the outer lead and a dummy outer lead in the stacked semiconductor package may have substantially the same shape.
Abstract:
An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.
Abstract:
The present invention provides an apparatus for forming a solder wicking prevention zone operating when a connector member with a connector is processed using molten solder, to hinder the solder from spreading to a contact site of the connector in a wettable manner. The apparatus includes a main forming agent tank which stores a main forming agent used to form the solder wicking prevention zone, an ejection nozzle which ejects the main forming agent stored in the main forming agent tank, and a direction control section which controls an ejection direction of the main forming agent ejected by the ejection nozzle. The direction control section controls the ejection direction of the main forming agent ejected by the ejection nozzle, so as to apply the main forming agent to a predetermined position on the connector member to form the solder wicking prevention zone.
Abstract:
A microelectronic device package that includes a microelectronic device encapsulated within a packaging material. The microelectronic device package also includes a lead attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.
Abstract:
A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.