公开(公告)号：US20060027925A1

公开(公告)日：2006-02-09

申请号：US11024916

申请日：2004-12-28

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC: H01L29/788

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

Abstract translation: 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

公开(公告)号：US06706629B1

公开(公告)日：2004-03-16

申请号：US10338120

申请日：2003-01-07

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.

Abstract translation: 提供了一种新的方法来产生包括铜的金属互连。 本发明的第一实施例提供了铜掺杂层的应用。 本发明的第二个实施例提供了在介质层中形成的开口的表面上沉积作为隔离膜的氮化硅层，然后从开口的底部去除氮化硅层，随后沉积 在该开口的表面上的铜掺杂合金种子层，然后在铜合金种子层上镀一层铜。

公开(公告)号：US09418876B2

公开(公告)日：2016-08-16

申请号：US13224575

申请日：2011-09-02

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US08816498B2

公开(公告)日：2014-08-26

申请号：US13189127

申请日：2011-07-22

Applicant: Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/485 ,  H01L21/768

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

公开(公告)号：US08779599B2

公开(公告)日：2014-07-15

申请号：US13298126

申请日：2011-11-16

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract translation: 一种器件包括底部芯片和结合到底部芯片的有源顶部管芯。 虚设裸片连接到底部芯片。 虚设裸片与底部芯片电绝缘。

公开(公告)号：US20130056865A1

公开(公告)日：2013-03-07

申请号：US13224575

申请日：2011-09-02

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L23/498

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US20110304042A1

公开(公告)日：2011-12-15

申请号：US12846260

申请日：2010-07-29

Applicant: Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US09159687B2

公开(公告)日：2015-10-13

申请号：US13572302

申请日：2012-08-10

Applicant: Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract translation: 用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

公开(公告)号：US08922004B2

公开(公告)日：2014-12-30

申请号：US12846260

申请日：2010-07-29

Applicant: Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US08698308B2

公开(公告)日：2014-04-15

申请号：US13362913

申请日：2012-01-31

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L29/40

CPC classification number: H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a α ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

Abstract translation: 用于形成凸块结构的机构能够在芯片和基板之间形成凸块结构，消除或降低焊料短路，焊剂残留物和底部填充物中的空隙的风险。 可以通过将粘合凸块结构中的铜柱的总高度除以接合的凸块结构的间隙来限定的α比来限定下限，以避免短路。 也可以建立一个下限以排除芯片封装以避免焊剂残留和底部填充空隙形成。 此外，由于制造工艺限制，铜柱凸起的纵横比具有下限以避免不足的间隙和更高的极限。 通过遵循适当的凸块设计和工艺指南，芯片封装的产量和可靠性可能会增加。