公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US10121690B2

公开(公告)日：2018-11-06

申请号：US14757589

申请日：2015-12-23

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L21/00 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.

公开(公告)号：US09988262B2

公开(公告)日：2018-06-05

申请号：US15704537

申请日：2017-09-14

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Joachim Mahler ,  Daniel Porwol ,  Alfred Sigl

IPC: B81C1/00

CPC classification number: B81C1/00047 ,  B81C1/00666 ,  B81C2201/0125 ,  B81C2201/013 ,  B81C2203/0118 ,  B81C2203/0127

Abstract: A method for fabricating an electronic device is disclosed. In one example, the method comprises providing a semiconductor wafer, forming a plurality of cavities into the semiconductor wafer, filling a stabilization material into the cavities, fabricating a temporary panel by applying a cap sheet onto the semiconductor wafer, the cap sheet covering the cavities, singulating the temporary panel into a plurality of semiconductor devices, fabricating an embedded wafer by embedding the semiconductor devices in an encapsulant, removing the cap sheet of each one of the semiconductor devices, and singulating the embedded wafer into a plurality of electronic devices.

公开(公告)号：US09986636B2

公开(公告)日：2018-05-29

申请号：US15476235

申请日：2017-03-31

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Ralf Otremba

IPC: H05K3/02 ,  H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/036 ,  H05K1/0203 ,  H05K1/032 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/007 ,  H05K3/0094 ,  H05K3/02 ,  H05K3/105 ,  H05K3/4038 ,  H05K3/4626 ,  H05K2201/0104 ,  H05K2201/0129 ,  H05K2201/0215 ,  H05K2201/0224 ,  H05K2201/0281 ,  H05K2203/107 ,  H05K2203/1136 ,  Y10T29/49126 ,  Y10T428/24909

Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer. The polymer includes at least one of a carbon layer structure and a carbon-like layer structure.

公开(公告)号：US09559078B2

公开(公告)日：2017-01-31

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US09540539B2

公开(公告)日：2017-01-10

申请号：US14287231

申请日：2014-05-27

Applicant: Infineon Technologies AG

Inventor： Swee Kah Lee ,  Joachim Mahler ,  Chew Theng Tai ,  Yik Yee Tan ,  Soon Lock Goh ,  Poh Cheng Lim ,  Jagen Krishnan ,  Peh Hean Teh

IPC: C09D179/04 ,  H01L23/29 ,  C09D5/08 ,  C09D163/00 ,  H01L21/56 ,  C08G14/06 ,  C09D161/34

CPC classification number: C09D179/04 ,  C08G14/06 ,  C09D5/002 ,  C09D5/08 ,  C09D161/34 ,  C09D163/00 ,  H01L21/565 ,  H01L23/296 ,  H01L23/3142 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  C08K5/544 ,  C08L63/00

Abstract: A primer composition is provided. The primer composition includes at least one bi- or multi-functional benzoxazine compound; and at least one compound including a functional group having affinity for a metallic surface, and a cross-linkable group. A method of forming a primer layer on a semiconductor device, and a method of encapsulating a semiconductor device are also provided.

Abstract translation: 提供底漆组合物。 底漆组合物包括至少一种双官能或多官能苯并恶嗪化合物; 和至少一种包含对金属表面具有亲和性的官能团的化合物和可交联基团。 还提供了在半导体器件上形成底漆层的方法以及封装半导体器件的方法。

公开(公告)号：US09530754B2

公开(公告)日：2016-12-27

申请号：US14880373

申请日：2015-10-12

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/48 ,  H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/495 ,  H01L23/00 ,  H01L23/492 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供芯片封装。 芯片封装可以包括导电载体; 至少一个第一芯片，包括第一侧和与第一侧相对的第二侧，其第二侧与导电载体电接触; 在所述导电载体的至少一部分上方以及所述芯片的第一侧的至少一部分上的绝缘层; 至少一个第二芯片布置在所述绝缘层上并且靠近所述第一芯片; 封装材料在第一芯片和第二芯片上; 以及电触头，其通过封装材料延伸到至少一个第一芯片的至少一个触点和至少一个第二芯片的至少一个触点。

公开(公告)号：US09530752B2

公开(公告)日：2016-12-27

申请号：US14076976

申请日：2013-11-11

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Petteri Palm ,  Joachim Mahler

IPC: H05K13/02 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L24/24 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant, and forming electrically conductive contacts for electrically contacting the at least partially encapsulated electronic chips.

Abstract translation: 一种方法，其包括将多个电子芯片布置在由芯片的相应表面部分限定的多个芯片容置空腔中，以及由布置在基板上的导电框架中的多个孔中的相应一个孔限定的壁， 至少部分地通过密封剂将所述电子芯片封装在所述芯片容纳腔中，以及形成用于电接触所述至少部分封装的电子芯片的导电触点。

公开(公告)号：US09385107B2

公开(公告)日：2016-07-05

申请号：US13959712

申请日：2013-08-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/074 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49827 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/08168 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material.

Abstract translation: 一种器件包括：衬底，其包括电绝缘芯，布置在衬底的第一主表面上的第一导电材料和布置在与第一主表面相对的衬底的第二主表面上的第二导电材料。 该装置还包括从第一主表面延伸到第二主表面并且电耦合第一导电材料和第二导电材料的导电连接，第一半导体芯片，布置在第一主表面上并电耦合到第一导电材料 导电材料和布置在第二主表面上并电耦合到第二导电材料的第二半导体芯片。

公开(公告)号：US20160181496A1

公开(公告)日：2016-06-23

申请号：US14579154

申请日：2014-12-22

Applicant: Infineon Technologies AG

Inventor： Christian Kegler ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Guenther Ruhl ,  Joachim Mahler

IPC: H01L35/04 ,  H01L35/14 ,  H01L35/18

CPC classification number: G01K7/16 ,  H01L29/16 ,  H01L29/1602 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L35/04 ,  H01L35/14 ,  H01L35/18

Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.

Abstract translation: 提供温度传感器装置和相应的方法。 温度传感器可以包括在温度范围内基本上不导电的第一层和在温度范围内具有变化的电阻的第二层。