公开(公告)号：US20180076142A1

公开(公告)日：2018-03-15

申请号：US15816743

申请日：2017-11-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Yaojian Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

公开(公告)号：US20170271241A1

公开(公告)日：2017-09-21

申请号：US15611110

申请日：2017-06-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu ,  Il Kwon Shim ,  Yaojian Lin ,  Won Kyoung Choi

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias.

公开(公告)号：US20170260043A1

公开(公告)日：2017-09-14

申请号：US15610997

申请日：2017-06-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Il Kwon Shim

IPC: B81B7/00

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

公开(公告)号：US20170110599A1

公开(公告)日：2017-04-20

申请号：US15394337

申请日：2016-12-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L31/0203 ,  H01L27/146 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L31/0203 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14698 ,  H01L31/02005 ,  H01L31/1876 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4038 ,  H05K2203/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.

公开(公告)号：US11842991B2

公开(公告)日：2023-12-12

申请号：US16990887

申请日：2020-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  OhHan Kim ,  HeeSoo Lee ,  HunTeak Lee ,  InSang Yoon ,  Il Kwon Shim

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/50

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L23/552 ,  H01L24/17 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/1146 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48179 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/97 ,  H01L2224/81

Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.

公开(公告)号：US11342278B2

公开(公告)日：2022-05-24

申请号：US17008997

申请日：2020-09-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SungWon Cho ,  ChangOh Kim ,  Il Kwon Shim ,  InSang Yoon ,  KyoungHee Park

IPC: H01L23/34 ,  H01L23/28 ,  H01L21/00 ,  H05K7/20 ,  H01L23/552 ,  H01L23/00 ,  H01L23/36 ,  H01L23/522 ,  H01L23/50 ,  H01L23/60 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L23/367

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US20200373289A1

公开(公告)日：2020-11-26

申请号：US16990887

申请日：2020-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  OhHan Kim ,  HeeSoo Lee ,  HunTeak Lee ,  InSang Yoon ,  Il Kwon Shim

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.

公开(公告)号：US20180261569A1

公开(公告)日：2018-09-13

申请号：US15976455

申请日：2018-05-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  OhHan Kim ,  HeeSoo Lee ,  HunTeak Lee ,  InSang Yoon ,  Il Kwon Shim

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/552

Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.

公开(公告)号：US09978665B2

公开(公告)日：2018-05-22

申请号：US15611110

申请日：2017-06-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu ,  Il Kwon Shim ,  Yaojian Lin ,  Won Kyoung Choi

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias.

公开(公告)号：US09865554B2

公开(公告)日：2018-01-09

申请号：US14955033

申请日：2015-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03001 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/3318

Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.