公开(公告)号：US07955893B2

公开(公告)日：2011-06-07

申请号：US12023921

申请日：2008-01-31

申请人： Tao Feng ,  François Hébert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  François Hébert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L21/00

CPC分类号： H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US20080182387A1

公开(公告)日：2008-07-31

申请号：US11701561

申请日：2007-01-31

申请人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

发明人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/288 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。

公开(公告)号：US20080166837A1

公开(公告)日：2008-07-10

申请号：US11652385

申请日：2007-01-10

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： H01L21/44 ,  H01L21/00

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/013

摘要： A power MOSFET wafer level chip-scale packaging method is disclosed. The method includes the steps of electroless plating a wafer backside and a plurality of contact pads on a wafer front side and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies. In an alternative embodiment, the method includes the steps of providing a permanent protective layer on a wafer backside, electroless plating a plurality of contact pads on a wafer front side, and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies.

摘要翻译： 公开了功率MOSFET晶片级芯片级封装方法。 该方法包括在将晶片切割成多个功率MOSFET管芯之前，在晶片正面侧上化学镀电晶片背面和多个接触焊盘并在镀覆的多个接触焊盘上形成焊球。 在替代实施例中，该方法包括以下步骤：在晶片背面上提供永久性保护层，在晶片正面侧面化学镀覆多个接触焊盘，以及在将晶片切割成晶片之前在镀覆的多个接触焊盘上形成焊球 多个功率MOSFET管芯。

公开(公告)号：US09731242B2

公开(公告)日：2017-08-15

申请号：US15028478

申请日：2013-11-06

申请人： XiaoShan Zhou ,  Ming Sun ,  Ji Lei

发明人： XiaoShan Zhou ,  Ming Sun ,  Ji Lei

IPC分类号： B01D53/047 ,  B01D53/06

CPC分类号： B01D53/06 ,  B01D53/047 ,  B01D2253/108 ,  B01D2253/116 ,  B01D2259/40003

摘要： A pressure swing adsorption apparatus having: a housing with an arc-shaped inner surface, the housing being arranged with at least one gas inlet, at least one exhaust port and at least one gas outlet for discharging the separated gas; a rotor arranged in the housing, at least two contact ends being arranged on the rotor for maintaining a non-stop sliding contact with the inner surface of the housing, individual cavities, i.e., air cavities between the adjacent contact ends and formed between the external surface of the rotor and the inner surface of the housing, and each air cavity being separated by the contact ends; adsorption chambers set inside the rotor as parts of the rotor and rotated along with the rotor, molecular sieves being loaded in the interior of the adsorption chambers, and the adsorption chambers being provided with screen openings for connection with the air cavities.

公开(公告)号：US08680658B2

公开(公告)日：2014-03-25

申请号：US12130663

申请日：2008-05-30

申请人： Lei Shi ,  Kai Liu ,  Ming Sun

发明人： Lei Shi ,  Kai Liu ,  Ming Sun

IPC分类号： H01L23/495

CPC分类号： H01L23/49524 ,  H01L23/4334 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/544 ,  H01L24/28 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers.

摘要翻译： 用于半导体器件封装的夹子可以包括通过一个或多个导电桥彼此电连接的两个或更多个分离的导电指状物。 至少手指的第一端适于与引线框架电接触。 桥适于提供与半导体器件的顶部半导体区域的电连接，并且还可以在手指的顶表面暴露时提供散热路径。 半导体器件封装可以包括夹子以及半导体器件和引线框架。 半导体器件可以分别在顶表面和底表面上具有第一半导体区域和半导体区域。 夹子可以在桥接处电连接到顶部半导体区域，并且在至少一个手指的第一端处电连接到引线框架。

公开(公告)号：US08670211B1

公开(公告)日：2014-03-11

申请号：US13164991

申请日：2011-06-21

申请人： Ming Sun ,  Jose A. Medina ,  Keith Y. Sasaki ,  Ming Jiang

发明人： Ming Sun ,  Jose A. Medina ,  Keith Y. Sasaki ,  Ming Jiang

IPC分类号： G11B5/127 ,  C25D3/00

CPC分类号： G11B5/3143 ,  C25D3/562 ,  C25D5/18 ,  C25D7/001 ,  G11B5/3163 ,  H01F41/26

摘要： A method and system plates CoFeX, where X is an insertion metal. The method and system include providing a plating solution including hydroxymethyl-p-tolylsulfone (HPT). The plating solution being configured to provide a CoFeX film having a high saturation magnetic flux density of greater than 2.3 Tesla and not more than 3 weight percent of X. The method and system also include plating the CoFeX film on a substrate in the plating solution. In some aspects, the plated CoFeX film may be used in structures such as main poles of a magnetic recording head.

摘要翻译： 一种方法和系统板CoFeX，其中X是插入金属。 该方法和系统包括提供包含羟甲基对甲苯砜（HPT）的电镀溶液。 电镀溶液被配置为提供具有大于2.3特斯拉的高饱和磁通密度和不大于X重量百分比的X的高的饱和磁通密度的CoFeX膜。该方法和系统还包括在电镀液中的基底上电镀CoFeX膜。 在一些方面，电镀CoFeX膜可以用于诸如磁记录头的主极的结构中。

公开(公告)号：US08497160B2

公开(公告)日：2013-07-30

申请号：US13560786

申请日：2012-07-27

申请人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L21/60

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 制造焊料顶部器件的方法包括将顶部金属层光刻地图案化成接触区域和接触增强区域; 然后使用用于增加的复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US20130006982A1

公开(公告)日：2013-01-03

申请号：US13497857

申请日：2010-06-03

申请人： Ming Sun

发明人： Ming Sun

IPC分类号： G06F17/30

CPC分类号： G06F11/3476 ,  G06F11/3409 ,  G06F17/30339 ,  H04L41/0823 ,  H04L41/0853

摘要： A method and system for storing performance data are disclosed, and the method includes: during a process of adding a collection point, a system creating a data subtable in real time according to the number of added collection points and a predetermined maximum number of collection points of the data subtable; and storing the performance data of the collection point into the created data subtable, and storing the corresponding relationship between the collection point and the data subtable.

摘要翻译： 公开了一种存储性能数据的方法和系统，该方法包括：在添加收集点的过程中，根据添加的收集点的数量和预定的最大数量的收集点，实时地生成数据的系统 的数据子表; 并将所述收集点的演奏数据存储在所生成的数据中，并且存储所述收集点和所述数据之间的对应关系。

公开(公告)号：US08343801B2

公开(公告)日：2013-01-01

申请号：US13278240

申请日：2011-10-21

申请人： Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Venkatram Venkatasamy ,  Philip George Pitcher ,  Nurul Amin

发明人： Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Venkatram Venkatasamy ,  Philip George Pitcher ,  Nurul Amin

IPC分类号： H01L21/00 ,  H01L21/16

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 电绝缘氧化物层将离子导体固体电解质材料与电化学活性电极分离。

公开(公告)号：US08334165B2

公开(公告)日：2012-12-18

申请号：US12761899

申请日：2010-04-16

申请人： Haiwen Xi ,  Ming Sun ,  Dexin Wang ,  Shuiyuan Huang ,  Michael Tang ,  Song S. Xue

发明人： Haiwen Xi ,  Ming Sun ,  Dexin Wang ,  Shuiyuan Huang ,  Michael Tang ,  Song S. Xue

IPC分类号： H01L21/00

CPC分类号： H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/143 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1658 ,  H01L45/1675

摘要： Methods for making a programmable metallization memory cell are disclosed.

摘要翻译： 公开了制造可编程金属化存储单元的方法。