公开(公告)号：US20170076981A1

公开(公告)日：2017-03-16

申请号：US15364160

申请日：2016-11-29

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L21/268 ,  H01L21/263

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和与第一表面相对的第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面。 隔离层和导电垫在一起具有第二通孔，使得激光阻挡件通过第二通孔露出。 再分配层位于第三表面，第二通孔的侧壁和激光停止器上。

公开(公告)号：US20170018590A1

公开(公告)日：2017-01-19

申请号：US15181291

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括感测装置。 芯片封装还包括设置在感测装置上并电连接到感测装置的第一导电结构。 芯片封装还包括设置在感测装置上的芯片和第二导电结构。 该芯片包括集成电路器件。 第二导电结构位于芯片上并与集成电路器件和第一导电结构电连接。 此外，芯片封装包括覆盖感测装置和芯片的绝缘层。 绝缘层具有孔。 第一导电结构位于孔底部。 绝缘层的顶表面与第二导电结构的顶表面共面。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20160233260A1

公开(公告)日：2016-08-11

申请号：US15013135

申请日：2016-02-02

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU

IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/0216

CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/1868 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes a first substrate including a device region and having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the second surface of the first substrate and includes a conducting pad structure connected to the device region, and the first substrate completely covers the conducting pad structure. A second substrate is disposed on the second surface of the first substrate and the dielectric layer is located between the first substrate and the second substrate. The second substrate has a first opening exposing a surface of the conducting pad structure, and a redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure. A method for forming the chip package is also provided.

Abstract translation: 本发明的一个实施例提供一种芯片封装，其包括包括器件区域并具有第一表面和与其相对的第二表面的第一衬底。 电介质层设置在第一衬底的第二表面上，并且包括连接到器件区域的导电焊盘结构，并且第一衬底完全覆盖导电焊盘结构。 第二基板设置在第一基板的第二表面上，并且电介质层位于第一基板和第二基板之间。 第二基板具有暴露导电焊盘结构的表面的第一开口，并且再分配层保形地设置在第一开口的侧壁和暴露的导电焊盘结构的表面上。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20160211233A1

公开(公告)日：2016-07-21

申请号：US14994537

申请日：2016-01-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0549 ,  H01L2924/10156 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0231 ,  H01L2224/48

Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

Abstract translation: 提供了一个芯片模块。 芯片模块包括具有上表面，下表面和侧壁的芯片。 芯片包括与上表面相邻的信号焊盘区域。 凹部沿着芯片的侧壁从上表面向下表面延伸。 再分配层电连接到信号焊盘区域并延伸到凹部中。 电路板位于上表面和下表面之间并延伸到凹槽中。 导电结构位于凹部中并将电路板电连接到再分布层。 还提供了一种用于形成芯片模块的方法。

公开(公告)号：US20160204061A1

公开(公告)日：2016-07-14

申请号：US14992776

申请日：2016-01-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

IPC: H01L23/522 ,  H01L21/304 ,  H01L21/268 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G06K9/0002 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5283 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.

Abstract translation: 一种芯片封装，包括芯片，第一通孔，导电结构，第一隔离层，第二通孔和第一导电层。 第一通孔从第二表面延伸到第一表面以暴露导电焊盘，并且导电结构在第二表面上并延伸到第一通孔以接触导电焊盘。 导电结构包括第二导电层和激光器塞。 第一隔离层位于第二表面上并覆盖导电结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光阻挡件，并且第一导电层在第三表面上并延伸到第二通孔以接触激光器塞。

公开(公告)号：US20150137341A1

公开(公告)日：2015-05-21

申请号：US14540460

申请日：2014-11-13

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L23/5386 ,  B81B7/0064 ,  B81B2207/096 ,  H01L21/561 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/29011 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48471 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.

Abstract translation: 提供了包括具有第一表面和与其相对的第二表面的第一基板的芯片封装。 第一基板具有微电元件和与第一表面相邻的多个导电垫。 第一基板具有分别暴露每个导电垫的一部分的多个开口。 第二基板设置在第一表面上。 封装层设置在第一表面上并覆盖第二基板。 再分配层设置在第二表面上并延伸到开口中以电连接导电垫。

公开(公告)号：US20140193950A1

公开(公告)日：2014-07-10

申请号：US14207247

申请日：2014-03-12

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Bai-Yao LOU ,  Ying-Nan WEN ,  Chien-Hung LIU

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

Abstract translation: 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US20130328147A1

公开(公告)日：2013-12-12

申请号：US13912792

申请日：2013-06-07

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Ying-Nan WEN ,  Tsang-Yu LIU

IPC: H01L31/02 ,  H01L31/0232

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。