公开(公告)号：US20140021583A1

公开(公告)日：2014-01-23

申请号：US13551676

申请日：2012-07-18

申请人： Sut-I Lo ,  Ching-Wen Hsiao ,  Hsu-Hsien Chen ,  Chen-Shien Chen

发明人： Sut-I Lo ,  Ching-Wen Hsiao ,  Hsu-Hsien Chen ,  Chen-Shien Chen

IPC分类号： H01L29/92 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/12105 ,  H01L2224/2413 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00

摘要： A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.

摘要翻译： 封装包括管芯，密封剂和电容器。 包装具有包装第一侧和包装第二侧。 模具具有对应于封装第一侧的管芯第一侧，并且具有对应于封装第二侧的管芯第二侧。 模具第一面与模具第二面相对。 密封剂围绕着模具。 电容器包括密封剂中的第一板和第二板，并且第一板和第二板的相对表面在从封装第一侧到封装第二侧的方向上延伸。 外部导电连接器附接到封装第一侧和封装第二侧中的至少一个。

公开(公告)号：US20130241052A1

公开(公告)日：2013-09-19

申请号：US13420405

申请日：2012-03-14

申请人： Wei Sen Chang ,  Ching-Wen Hsiao ,  Chen-Shien Chen

发明人： Wei Sen Chang ,  Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L24/19 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05553 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.

摘要翻译： 焊接在封装结构上封装的插槽连接上。 一种设备包括：具有前侧表面和后侧表面的基板; 设置在前侧面和后侧表面中的至少一个上的第一钝化层; 形成在所述第一钝化层中的至少一个通孔; 布置在所述第一钝化层上方的导体层，耦合到所述至少一个通孔并在所述第一钝化层的表面上形成导电迹线; 形成在所述导体层上的第二钝化层; 以及形成在所述第二钝化层中并且暴露所述导电迹线的一部分以用于接收焊料连接器的至少一个狭槽开口。 在另外的实施例中，衬底可以是半导体晶片。 公开了形成结构的方法。

公开(公告)号：US20130009303A1

公开(公告)日：2013-01-10

申请号：US13178161

申请日：2011-07-07

申请人： Pei-Chun Tsai ,  Sheng-Yu Wu ,  Ching-Wen Hsiao ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Pei-Chun Tsai ,  Sheng-Yu Wu ,  Ching-Wen Hsiao ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/48

摘要： A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections.

摘要翻译： 封装封装（PoP）包括具有多个衬底迹线的衬底，通过多个贴合在轨迹连接与衬底连接的衬底顶部的第一功能芯片，以及顶部上的第二功能芯片 的第一功能芯片，直接连接到基板。 另一个封装封装（PoP）包括：具有多个衬底迹线的衬底，通过在连接的SMD焊盘上形成的多个焊接掩模限定（SMD）连接到衬底的顶部上的第一功能芯片 焊料凸点，以及位于第一功能芯片顶部的第二功能芯片，通过多个贴合在线跟踪连接直接连接到基板。

公开(公告)号：US20110186986A1

公开(公告)日：2011-08-04

申请号：US12697008

申请日：2010-01-29

申请人： Yao-Chun Chuang ,  Chen-Cheng Kuo ,  Ching-Wen Hsiao ,  Chen-Shien Chen

发明人： Yao-Chun Chuang ,  Chen-Cheng Kuo ,  Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L21/768 ,  H01L23/498 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16503 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.

摘要翻译： 提供了一种用于半导体器件的T形柱。 T形柱具有凸起下金属化（UBM）部分和从UBM部分延伸的柱部分。 UBM部分和支柱部分可以由相同的材料或不同的材料形成。 在一个实施例中，具有T形柱的衬底（例如管芯，晶片，印刷电路板，封装衬底等）被附接到另一个衬底（例如管芯，晶片，印刷电路板， 包装衬底等。 T形柱可以具有预先形成在柱部上的焊料材料，使得柱部分暴露或者使得柱部分被焊料材料覆盖。 在另一个实施例中，T形柱可以形成在一个基底上，并且焊料材料形成在另一个基底上。

公开(公告)号：US20110101526A1

公开(公告)日：2011-05-05

申请号：US12619468

申请日：2009-11-16

申请人： Ching-Wen Hsiao ,  Jiun Yi Wu ,  Ru-Ying Huang ,  Chen-Shien Chen

发明人： Ching-Wen Hsiao ,  Jiun Yi Wu ,  Ru-Ying Huang ,  Chen-Shien Chen

IPC分类号： H01L23/52 ,  H01L23/538

CPC分类号： H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.

摘要翻译： 集成电路结构包括第一工件和第二工件。 第一工件包括半导体衬底和半导体衬底上的铜凸块。 第二工件包括接合垫。 焊料在第一工件和第二工件之间并相邻，其中焊料将铜凸块电连接到接合焊盘。 焊料包括钯。

公开(公告)号：US20110049706A1

公开(公告)日：2011-03-03

申请号：US12831819

申请日：2010-07-07

申请人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

发明人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/13 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/818 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552

摘要： An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

摘要翻译： 集成电路结构包括半导体衬底; 穿过半导体衬底的导电通孔（TSV）; 以及覆盖半导体衬底并电连接到导电通孔的含铜柱。

公开(公告)号：US08871609B2

公开(公告)日：2014-10-28

申请号：US12818362

申请日：2010-06-18

申请人： Chen-Hua Yu ,  Kuo-Ching Hsu ,  Chen-Shien Chen ,  Ching-Wen Hsiao

发明人： Chen-Hua Yu ,  Kuo-Ching Hsu ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/683 ,  H01L21/18 ,  H01L21/26 ,  H01L21/265

CPC分类号： H01L21/187 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T428/1476

摘要： A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

摘要翻译： 薄晶片处理结构包括半导体晶片，可通过施加能量释放的释放层，可通过溶剂除去的粘合剂层和载体，其中通过涂覆或层压将剥离层施加在载体上， 通过涂布或层压将粘合剂层施加在半导体晶片上，半导体晶片和载体与剥离层和粘合剂层粘合在一起。 该方法包括在载体上施加剥离层，在半导体晶片上施加粘合剂层，粘合载体和半导体晶片，通过在释放层上施加能量来释放载体，例如， UV或激光，并且通过溶剂清洁半导体的表面以除去粘合剂层的任何残余物。

公开(公告)号：US08766441B2

公开(公告)日：2014-07-01

申请号：US13420405

申请日：2012-03-14

申请人： Wei Sen Chang ,  Ching-Wen Hsiao ,  Chen-Shien Chen

发明人： Wei Sen Chang ,  Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L21/44 ,  H01L23/498

CPC分类号： H01L24/19 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05553 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.

摘要翻译： 焊接在封装结构上的封装上的插槽连接上。 一种设备包括：具有前侧表面和后侧表面的基板; 设置在前侧面和后侧表面中的至少一个上的第一钝化层; 形成在所述第一钝化层中的至少一个通孔; 布置在所述第一钝化层上方的导体层，耦合到所述至少一个通孔并在所述第一钝化层的表面上形成导电迹线; 形成在所述导体层上的第二钝化层; 以及形成在所述第二钝化层中并且暴露所述导电迹线的一部分以用于接收焊料连接器的至少一个狭槽开口。 在另外的实施例中，衬底可以是半导体晶片。 公开了形成结构的方法。

公开(公告)号：US08178970B2

公开(公告)日：2012-05-15

申请号：US12623925

申请日：2009-11-23

申请人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ching-Wen Hsiao

发明人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ching-Wen Hsiao

IPC分类号： H01L23/488

CPC分类号： H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/206 ,  H01L2924/207

摘要： A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.

摘要翻译： 公开了一种倒装芯片封装组件和集成电路器件。 示例性的倒装芯片封装组件包括第一基板; 第二基板; 以及设置在第一基板和第二基板之间的接合结构。 每个接头结构包括在第一基板和第二基板之间的互连柱和在互连柱和第二基板之间的接合焊料，其中互连柱呈现宽度和第一高度。 间距定义每个关节结构之间的距离。 第一高度小于音高的一半。

公开(公告)号：US08101499B2

公开(公告)日：2012-01-24

申请号：US12751512

申请日：2010-03-31

申请人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

发明人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC分类号： H01L21/30

摘要： An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.