公开(公告)号：US5378314A

公开(公告)日：1995-01-03

申请号：US77298

申请日：1993-06-15

Applicant: Walter Schmidt ,  Marco Martinelli

Inventor： Walter Schmidt ,  Marco Martinelli

IPC: C23F1/00 ,  H05K1/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  B29C37/00

CPC classification number: H05K3/42 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652

Abstract: A method for producing aligned passages through substrate materials, in which the projection of the inlet and outlet openings does not coincide, uses displaced application of etching windows on opposite sides and corresponding pronounced under-etching of these windows. By applying displaced etching windows on both sides of the substrate and through-etching the substrate through these windows, `oblique` passages are obtained through the substrate. By a suitable location of the windows it is also possible to produce branched passages with more than one outlet opening.

Abstract translation: 用于产生通过基底材料的对准的通道的方法，其中入口和出口的突出部不重合，使用在相对侧上移动施加蚀刻窗口并且对应于这些窗口的相当明显的下蚀刻。 通过在基板的两面上施加位移蚀刻窗口，并通过这些窗口对基板进行蚀刻，通过基板获得“倾斜”通道。 通过窗口的合适位置，也可以产生具有多于一个出口开口的分支通道。

公开(公告)号：US5347712A

公开(公告)日：1994-09-20

申请号：US76191

申请日：1993-06-14

Applicant: Nobuyuki Yasuda ,  Toshio Tamura ,  Hiroshi Toi ,  Akio Mishima

Inventor： Nobuyuki Yasuda ,  Toshio Tamura ,  Hiroshi Toi ,  Akio Mishima

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/0044 ,  H05K1/115 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/09845 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K3/429 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer wiring board and a method for manufacturing the same are disclosed. The wiring board comprises an insulating substrate having a first and second conductor layers formed on major surfaces of the insulating substrate, a blind hole formed through the first conductor layer and the insulating substrate to expose the second conductor layer at the bottom of the blind hole, and a connecting conductor provided to cover the exposed surface of the second conductor layer wall portion of the blind hole and the first conductor layer. Since the connecting conductor and the second conductor are made in surface contact, connection reliability is very much improved. The blind hole is made by blasting a fine abrasive powder beam to selectively remove the insulating substrate. The end of selective removal can be easily controlled by the difference of working speed against the insulating substrate and the conductor layer to successfully expose the second conductor layer at the bottom of the blind hole.

Abstract translation: 公开了一种多层布线板及其制造方法。 所述布线基板包括绝缘基板，所述绝缘基板具有形成在所述绝缘基板的主表面上的第一和第二导体层，通过所述第一导体层形成的盲孔和所述绝缘基板，以露出所述盲孔底部的所述第二导体层， 以及连接导体，被设置为覆盖盲孔的第二导体层壁部分和第一导体层的暴露表面。 由于连接导体和第二导体形成表面接触，所以连接可靠性得到非常大的改善。 盲孔通过喷射细磨料粉末束来选择性地去除绝缘基底而制成。 可以通过与绝缘基板和导体层的工作速度的差异容易地控制选择性去除的结束，以成功地暴露在盲孔底部的第二导体层。

公开(公告)号：US5320894A

公开(公告)日：1994-06-14

申请号：US702326

申请日：1991-05-20

Applicant: Shinichi Hasegawa

Inventor： Shinichi Hasegawa

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  B32B9/00

CPC classification number: H01L23/538 ,  H01L23/5384 ,  H05K1/115 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multilayer interconnection substrate having, e.g., first to third power interconnections provided with first to third interconnection layers. A first insulating layer is provided between the first and second interconnection layers, and a second insulating layer is provided between the second and third interconnection layers. A plurality of first via holes are provided at said first insulating layer and connect the first and second power interconnections and a plurality of second via holes are provided at said second insulating layer with their position being shifted from that of the first via holes and connect the second and third power interconnection.

Abstract translation: 具有例如设置有第一至第三互连层的第一至第三电源互连的多层互连衬底。 第一绝缘层设置在第一和第二互连层之间，第二绝缘层设置在第二和第三互连层之间。 多个第一通孔设置在所述第一绝缘层处并且连接第一和第二电源互连，并且多个第二通孔设置在所述第二绝缘层处，其位置与第一通孔的位置相连， 第二和第三电力互连。

公开(公告)号：US5197184A

公开(公告)日：1993-03-30

申请号：US580758

申请日：1990-09-11

Applicant: William R. Crumly ,  Christopher M. Schreiber ,  Haim Feigenbaum

Inventor： William R. Crumly ,  Christopher M. Schreiber ,  Haim Feigenbaum

IPC: H05K1/11 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/205 ,  H05K3/4007 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/0117 ,  H05K2203/0726 ,  Y10T29/49155 ,  Y10T29/49158

Abstract: A pressure-type contact for flexible or conventional wire cable terminations is fabricated from electroformed thin metallic wafers (100) in which one wafer is plated with a raised conductive interconnection feature (122). The electrical circuitry (118, 120) is made on a stainless steel mandrel (10, 10a) having a TEFLON pattern (16, 16a) on its surface that allows the desired electrical circuit (30, 32, 34, 30a, 32a, 34a, 78) to be electrolytically plated upon the conductive mandrel surface. The mandrel surface is formed with projecting features in the form of depressions (24, 24a) that will form a series of dots or raised interconnection features on the termination wafers. The mandrel also has projecting posts (76) for providing electrical connection through the substrate.

公开(公告)号：US5162144A

公开(公告)日：1992-11-10

申请号：US739269

申请日：1991-08-01

Applicant: Vernon L. Brown ,  Julia S. Johnson ,  Yaroslaw A. Magera

Inventor： Vernon L. Brown ,  Julia S. Johnson ,  Yaroslaw A. Magera

IPC: C23C18/16 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C23C18/20 ,  C23C18/28 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46

CPC classification number: C04B41/009 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C23C18/28 ,  H05K3/4661 ,  C04B2111/00844 ,  H05K2201/0236 ,  H05K2201/09509 ,  H05K2203/095 ,  H05K2203/1157 ,  H05K2203/125 ,  H05K3/0023 ,  H05K3/181 ,  H05K3/184 ,  H05K3/465 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A unique process metallizes a substrate surface using a reducing agent including a borohydride to reduce, in a starved reaction, metal oxide particles (300) substantially uniformly distributed and at a controlled concentration in a particle-filled resin (204) to produce catalytic island areas (301). The catalytic island areas (301) formed have a surface resistivity greater than 10.sup.6 ohms per square. These catalytic island areas (301) are then electrolessly metallized to a predetermined thickness, such that adjacent catalytic island areas (301) are interconnected and form metallic features, such as pads, vias (213), and conductors (210, 211 and 212). The starved reaction limits the reduction of metal oxide particles (300) to catalytic island areas (301) and prevents migration of reduced metal beyond each of the exposed surfaces of particle-filled resin (204) which are to be metallized.

Abstract translation: 独特的方法使用包括硼氢化物的还原剂金属化基底表面，以在饥饿的反应中将在基本上均匀分布并以受控浓度的金属氧化物颗粒（300）减少到填充颗粒的树脂（204）中以产生催化岛区 （301）。 形成的催化岛区域（301）具有大于106欧姆/平方的表面电阻率。 然后将这些催化岛区域（301）无电镀金属化至预定厚度，使相邻的催化岛区域（301）互连并形成金属特征，例如焊盘，通孔（213）和导体（210,211和212） 。 饥饿的反应将金属氧化物颗粒（300）的还原限制到催化岛区域（301），并且防止还原金属迁移到待金属化的颗粒填充树脂（204）的每个暴露表面之外。

公开(公告)号：US5053921A

公开(公告)日：1991-10-01

申请号：US601927

申请日：1990-10-23

Applicant: Gregory H. Nelson ,  Steven C. Lockard

Inventor： Gregory H. Nelson ,  Steven C. Lockard

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/64 ,  H05K3/00 ,  H05K3/20 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/4655 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/642 ,  H05K3/205 ,  H05K3/4673 ,  B23K2203/05 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09918 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/107 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/386 ,  H05K3/4644 ,  H05K3/4652

Abstract: An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture thereof are presented. The interconnect device has at least three layers of circuitry, one for signal transmission and two for voltage planes (power and ground). The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power and ground) plane layers.

Abstract translation: 本发明提供了一种用于电子部件的互连装置，例如集成电路，多芯片模块等及其制造方法。 互连器件具有至少三层电路，一层用于信号传输，另一层用于电压平面（电源和接地）。 互连器件是通过在不锈钢载体板上的加工制成的，以实现高引线数能力，具有精细的线宽和间距，以及精确的配准层到层。 激光钻孔用于定义信号和电压（电源和接地）平面层之间的互连通孔。

公开(公告)号：US5049974A

公开(公告)日：1991-09-17

申请号：US534038

申请日：1990-06-29

Applicant: Gregory H. Nelson ,  Sanford Lebow ,  Eugene Nogavich

Inventor： Gregory H. Nelson ,  Sanford Lebow ,  Eugene Nogavich

IPC: H01L23/14 ,  H01L23/498 ,  H05K3/00 ,  H05K3/20 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/4673 ,  H01L23/142 ,  H01L23/49894 ,  H05K3/205 ,  H05K3/4655 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09918 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/107 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/386 ,  H05K3/4644 ,  H05K3/4652

Abstract: An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture of such components are presented. The interconnect device has two layers of circuitry, one for signal transmission and one for voltage plane. The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power or ground) plane layers.

Abstract translation: 提出了一种用于诸如集成电路，多芯片模块等的电子部件的互连装置及其制造方法。 互连设备具有两层电路，一层用于信号传输，另一层用于电压平面。 互连器件是通过在不锈钢载体板上的加工制成的，以实现高引线数能力，具有精细的线宽和间距，以及精确的配准层到层。 激光钻孔用于定义信号和电压（电源或接地）平面层之间的互连通孔。

公开(公告)号：US5036431A

公开(公告)日：1991-07-30

申请号：US393013

申请日：1989-08-11

Applicant: Kazumasa Adachi ,  Shinji Takahashi ,  Kimitaka Hirabayashi

Inventor： Kazumasa Adachi ,  Shinji Takahashi ,  Kimitaka Hirabayashi

IPC: H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K1/114 ,  H05K1/141 ,  H05K1/144 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10871 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/368 ,  H05K3/4652

Abstract: A package for surface-mounted components according to the present invention includes a first board which includes contact portions formed on a front face side thereof for mounting the components to be surface-mounted thereon, and first through-holes electrically contiguous with the contact portions; a second board includes conductor pins provided on a rear face side thereof for establishing continuity with another board and second through-holes electrically contiguous with the conductor pins; and a conductor layer interposed between the first and second boards by which the first through-holes in the first board side and the second through-holes in the second board side are mutually electrically connected.

Abstract translation: 根据本发明的用于表面安装部件的包装包括第一板，其包括形成在其正面侧上的接触部分，用于安装要表面安装的部件，以及与接触部分电连接的第一通孔; 第二板包括设置在其背面侧的导体销，用于与另一个板形成连续性，并且与导体引脚电连接的第二通孔; 以及介于第一和第二板之间的导体层，第一板侧的第一通孔和第二板侧的第二通孔相互电连接。

公开(公告)号：US4980270A

公开(公告)日：1990-12-25

申请号：US71312

申请日：1987-07-09

Applicant: Jun Inasaka

Inventor： Jun Inasaka

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/0023 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K3/4644

Abstract: A printed circuit comprising a substrate, a first conductive circuit pattern thereon and an insulator on the first conductive circuit pattern. The insulator has a via hole which extends down to and is tapered toward the first conductive circuit pattern. A second conductive circuit pattern is formed on the side wall of the via hole and on a portion of the first conductive circuit pattern. The tapered via hole allows the second conductive circuit pattern to ensure excellent electrical contact with the first conductive circuit pattern.

Abstract translation: 一种印刷电路，包括衬底，其上的第一导电电路图案和第一导电电路图案上的绝缘体。 绝缘体具有朝向第一导电电路图案向下延伸并逐渐变细的通孔。 在通孔的侧壁和第一导电电路图案的一部分上形成第二导电电路图案。 锥形通孔允许第二导电电路图案确保与第一导电电路图案的良好的电接触。

公开(公告)号：US4964212A

公开(公告)日：1990-10-23

申请号：US404410

申请日：1989-09-08

Applicant: Patrice Deroux-Dauphin ,  Henri Sibuet ,  Thierry Dupeux

Inventor： Patrice Deroux-Dauphin ,  Henri Sibuet ,  Thierry Dupeux

IPC: H01L21/302 ,  B23K26/38 ,  G11B5/31 ,  H01L21/768 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40

CPC classification number: G11B5/3103 ,  B23K26/386 ,  H01L21/76898 ,  H05K3/0029 ,  H05K1/0306 ,  H05K2201/0326 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2203/0207 ,  H05K2203/1383 ,  H05K3/4076 ,  Y10S438/94 ,  Y10T29/49165

Abstract: According to the invention, blind holes (27) and not through-holes are produced. For this purpose, the substrate (10) to be pierced or perforated is previously covered with a layer (12) less absorbing for the laser perforating beam (26) than the substrate.Application to the production of electronic circuits, magnetic recording devices, etc.

Abstract translation: 根据本发明，制造盲孔（27）而不产生通孔。 为此目的，要刺穿或穿孔的基底（10）预先用比基底更少地吸收激光射孔束（26）的层（12）覆盖。 适用于生产电子电路，磁记录装置等