Probing a device
    33.
    发明申请
    Probing a device 失效
    探测设备

    公开(公告)号:US20050179455A1

    公开(公告)日:2005-08-18

    申请号:US10781369

    申请日:2004-02-18

    CPC classification number: G01R31/2886 G01R31/2887

    Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.

    Abstract translation: 电子设备移动到第一位置,使得电子设备的端子是与端子电接触的相邻探头。 然后电子设备水平或对角地移动,使得端子接触探针。 然后通过探头将测试数据传送到电子设备和从电子设备传送。

    Air Bridge Structures And Methods Of Making And Using Air Bridge Structures
    34.
    发明申请
    Air Bridge Structures And Methods Of Making And Using Air Bridge Structures 失效
    空气桥梁结构与制造和使用空气桥梁结构的方法

    公开(公告)号:US20070265795A1

    公开(公告)日:2007-11-15

    申请号:US11382458

    申请日:2006-05-09

    Applicant: Gaetan Mathieu

    Inventor: Gaetan Mathieu

    Abstract: A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons.

    Abstract translation: 根据本发明的一些实施例的探针卡组件可以包括测试器接口,其被配置为与测试控制器进行电连接,多个导电探针被设置成接触要测试的电子设备的端子,以及多个 连接测试仪接口和探头的导电数据路径。 数据路径中的至少一个可以包括空气桥结构迹线,其包括通过多个塔架与导电板间隔开的导电迹线。

    Methods for making plated through holes usable as interconnection wire or probe attachments

    公开(公告)号:US20060185164A1

    公开(公告)日:2006-08-24

    申请号:US11403138

    申请日:2006-04-11

    Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

    Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system
    36.
    发明申请
    Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system 审中-公开
    用于通过可用于在晶片测试系统中形成可移除衬底砖的结构的垂直供电的方法

    公开(公告)号:US20050108875A1

    公开(公告)日:2005-05-26

    申请号:US10723263

    申请日:2003-11-26

    Abstract: Methods are provided for making vertical feed through electrical connection structures in a substrate or tile. The vertical feed throughs are configured to make the tile attachable and detachable as a layer between other substrates. For example, the tile with vertical feedthroughs can form an easily detachable space transformer tile in a wafer test system. The vertical feed through paths are formed with one end of each feed through hole permanently encapsulating a first electrical contact, and a second end supporting another pluggable and unpluggable electrical probe contact. Decoupling capacitors can be further plugged into holes formed in close proximity to the vertical feed through holes to increase performance of the decoupling capacitor.

    Abstract translation: 提供了用于通过基底或瓦片中的电连接结构进行垂直馈送的方法。 垂直进料通道被配置成使得瓦片能够作为其它基底之间的层附着和拆卸。 例如,具有垂直馈通的瓦片可以在晶片测试系统中形成容易拆卸的空间变压器瓦片。 垂直进料通道形成有每个进料通孔的一端,其永久地密封第一电接触,第二端支撑另一可插拔和可拔出的电探针接触。 去耦电容器可以进一步插入靠近垂直馈通孔形成的孔中,以提高去耦电容的性能。

    Method of making connections to a semiconductor chip assembly
    38.
    发明授权
    Method of making connections to a semiconductor chip assembly 失效
    连接到半导体芯片组件的方法

    公开(公告)号:US5915752A

    公开(公告)日:1999-06-29

    申请号:US374559

    申请日:1995-05-08

    Abstract: A connection component for electrically connecting a semiconductor chip to support substrate incorporates a preferably dielectric supporting structure (70) defining gaps (40). Leads extend across these gaps so that the leads are supported both sides of the gap (66, 70). The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section (72) adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool which has features adapted to control the position of the lead.

    Abstract translation: PCT No.PCT / US93 / 06930 Sec。 371日期1995年5月8日 102(e)日期1995年5月8日PCT提交1993年7月23日PCT公布。 出版物WO94 / 03036 日期1994年2月3日用于将半导体芯片电连接到支撑衬底的连接部件包含限定间隙(40)的优选电介质支撑结构(70)。 引线延伸穿过这些间隙,使得引线被支撑在间隙(66,70)的两侧。 因此,引线可以通过将连接部件与芯片对准而大致对准芯片上的触点。 每个引线被布置成使得当向引线施加向下的力时,一端可相对于支撑结构移位。 这允许引线通过使每个引线与工具接合并将引线向下抵靠接触件而连接到芯片上的触点。 优选地,每个引线包括与间隙的一侧相邻的易碎部分(72),并且当引线与触点接合时,易碎部分断裂。 引线与芯片上的触点的最终对准由具有适于控制引线位置的特征的焊接工具提供。

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