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    Methods for making plated through holes usable as interconnection wire or probe attachments
    1.
    发明申请
    Methods for making plated through holes usable as interconnection wire or probe attachments 有权

    公开(公告)号：US20060185164A1

    公开(公告)日：2006-08-24

    申请号：US11403138

    申请日：2006-04-11

    Applicant: Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

    Inventor： Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

    IPC: H05K3/00

    CPC classification number: H05K3/42 ,  G01R1/06711 ,  G01R1/07307 ,  G01R3/00 ,  H05K3/308 ,  H05K2201/09836 ,  H05K2203/0338 ,  Y10T29/49117 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49194

    Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

    Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system
    2.
    发明申请
    Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system 审中-公开
    用于通过可用于在晶片测试系统中形成可移除衬底砖的结构的垂直供电的方法

    公开(公告)号：US20050108875A1

    公开(公告)日：2005-05-26

    申请号：US10723263

    申请日：2003-11-26

    Applicant: Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

    Inventor： Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

    IPC: G01R1/067 ,  G01R3/00 ,  H05K3/30 ,  H05K3/42 ,  H01R43/00

    CPC classification number: G01R1/06711 ,  G01R3/00 ,  H05K3/308 ,  H05K3/42 ,  H05K2201/09836 ,  H05K2203/0338 ,  Y10T29/49139 ,  Y10T29/49165 ,  Y10T29/49222

    Abstract: Methods are provided for making vertical feed through electrical connection structures in a substrate or tile. The vertical feed throughs are configured to make the tile attachable and detachable as a layer between other substrates. For example, the tile with vertical feedthroughs can form an easily detachable space transformer tile in a wafer test system. The vertical feed through paths are formed with one end of each feed through hole permanently encapsulating a first electrical contact, and a second end supporting another pluggable and unpluggable electrical probe contact. Decoupling capacitors can be further plugged into holes formed in close proximity to the vertical feed through holes to increase performance of the decoupling capacitor.

    Abstract translation: 提供了用于通过基底或瓦片中的电连接结构进行垂直馈送的方法。 垂直进料通道被配置成使得瓦片能够作为其它基底之间的层附着和拆卸。 例如，具有垂直馈通的瓦片可以在晶片测试系统中形成容易拆卸的空间变压器瓦片。 垂直进料通道形成有每个进料通孔的一端，其永久地密封第一电接触，第二端支撑另一可插拔和可拔出的电探针接触。 去耦电容器可以进一步插入靠近垂直馈通孔形成的孔中，以提高去耦电容的性能。

    Semiconductor chip assemblies and components with pressure contact
    4.
    发明授权
    Semiconductor chip assemblies and components with pressure contact 失效
    半导体芯片组件和压力接触部件

    公开(公告)号：US5414298A

    公开(公告)日：1995-05-09

    申请号：US38178

    申请日：1993-03-26

    Applicant: Gary Grube ,  Igor Khandros ,  Gaetan Mathieu

    Inventor： Gary Grube ,  Igor Khandros ,  Gaetan Mathieu

    IPC: H01L23/48 ,  H01L39/02

    CPC classification number: H01L24/72 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  Y10T29/49004 ,  Y10T29/4913

    Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.

    Abstract translation: 半导体芯片组件包括芯片，通过柔性引线永久地电连接到芯片的芯片和用于将端子偏压离开芯片的弹性元件或元件。 芯片与具有接触焊盘的基板永久地接合，使得端子设置在芯片和基板之间，并且端子在由弹性元件施加的力的影响下接合接触焊盘。 端子通常设置在柔性片状电介质插入件上，并且弹性元件设置在插入件和芯片之间。 可以在与基板接合之前测试芯片和端子的组件。 由于该组件与衬底的接合不涉及焊接或其它复杂的结合工艺，所以是可靠的。 组件可以非常紧凑，并且可以占据仅比芯片本身的面积稍大的区域。

    CONTACT TIP STRUCTURE FOR MICROELECTRONIC INTERCONNECTION ELEMENTS AND METHODS OF MAKING SAME
    5.
    发明申请
    CONTACT TIP STRUCTURE FOR MICROELECTRONIC INTERCONNECTION ELEMENTS AND METHODS OF MAKING SAME 审中-公开
    微电子互连元件的接点提示结构及其制作方法

    公开(公告)号：US20080116927A1

    公开(公告)日：2008-05-22

    申请号：US12020380

    申请日：2008-01-25

    Applicant: Thomas Dozier ,  Benjamin Eldridge ,  Igor Khandros ,  Gaetan Mathieu ,  Sheldon Taylor

    Inventor： Thomas Dozier ,  Benjamin Eldridge ,  Igor Khandros ,  Gaetan Mathieu ,  Sheldon Taylor

    IPC: G01R1/067 ,  G01R31/02

    CPC classification number: G01R1/06727 ,  G01R1/07342 ,  H01L2924/01074 ,  H01L2924/01078

    Abstract: Contact tip structures are fabricated on sacrificial substrates for subsequent joining to interconnection elements including composite interconnection elements, monolithic interconnection elements, tungsten needles of probe cards, contact bumps of membrane probes, and the like. The spatial relationship between the tip structures can lithographically be defined to very close tolerances. The metallurgy of the tip structures is independent of that of the interconnection element to which they are attached, by brazing, plating or the like. The contact tip structures are readily provided with topological (small, precise, projecting, non-planar) contact features, such as in the form of truncated pyramids, to optimize electrical pressure connections subsequently being made to terminals of electronic components. Elongate contact tip structures, adapted in use to function as spring contact elements without the necessity of being joined to resilient contact elements are described. Generally, the invention is directed to making (pre-fabricating) relatively ‘perfect’ contact tip structures (“tips”) and joining them to relatively ‘imperfect’ interconnection elements to improve the overall capabilities of resulting “tipped” interconnection elements.

    Abstract translation: 接触尖端结构被制造在牺牲衬底上，用于随后连接到包括复合互连元件，单片互连元件，探针卡的钨针，膜探针的接触凸块等的互连元件。 尖端结构之间的空间关系可以光刻地定义为非常接近的公差。 尖端结构的冶金独立于它们所连接的互连元件的冶金，通过钎焊，电镀等。 接触尖端结构容易地具有拓扑（小的，精确的，突出的，非平面的）接触特征，例如呈截锥形的形式，以优化随后对电子部件的端子进行的电压连接。 描述了适于用作弹簧接触元件而不需要接合到弹性接触元件的细长接触尖端结构。 通常，本发明旨在制造（预制）相对“完美”的接触尖端结构（“尖端”）并将它们连接到相对“不完美”的互连元件，以改善所产生的“尖端”互连元件的整体能力。

    Methods for making plated through holes usable as interconnection wire or probe attachments
    9.
    发明申请
    Methods for making plated through holes usable as interconnection wire or probe attachments 有权
    电镀通孔可用作互连线或探头附件的方法

    公开(公告)号：US20050108876A1

    公开(公告)日：2005-05-26

    申请号：US10723269

    申请日：2003-11-26

    Applicant: Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

    Inventor： Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

    IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H05K3/30 ,  H05K3/42 ,  H05K3/00 ,  H05K13/00

    CPC classification number: H05K3/42 ,  G01R1/06711 ,  G01R1/07307 ,  G01R3/00 ,  H05K3/308 ,  H05K2201/09836 ,  H05K2203/0338 ,  Y10T29/49117 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49194

    Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

    Abstract translation: 提供了用于制造用于插入和连接连接器探针的电镀通孔的方法。 在第一种方法中，通过将弯曲的可蚀刻线接合到第一衬底上形成弯曲的电镀通孔，用不可蚀刻的导电材料镀覆电线，用电介质材料包住电镀线以形成第二衬底， 衬底以暴露可蚀刻线，并蚀刻电线以留下镀通孔。 在第二种方法中，首先将涂覆有第一可蚀刻层的线接合到衬底上，然后将第二不可蚀刻镀层施加在第一层上，并且第一层被蚀刻掉，从而通过设置在内部的布线的孔通过电镀。 在第三实施例中，掩模材料层最初沉积在衬底上并被蚀刻以形成填充有牺牲填充材料的孔，然后去除掩模材料，电镀填充材料，进行研磨以除去一些电镀 露出填充材料，然后将填充材料蚀刻掉，留下电镀的连接孔。 探针可以附着到电镀通孔或连接孔，以产生弹性弹簧触点，以形成晶片探针卡组件。 通过将涂覆有电镀材料的扭转牺牲线支撑在基板中，并且随后蚀刻掉线来形成扭曲管镀通孔结构。

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