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    Method and apparatus for testing bumped die
    37.
    发明申请
    Method and apparatus for testing bumped die 审中-公开
    碰撞模具测试方法和装置

    公开(公告)号：US20050174134A1

    公开(公告)日：2005-08-11

    申请号：US11101220

    申请日：2005-04-07

    Applicant: James Wark

    Inventor： James Wark

    IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H05K3/32 ,  H05K3/40 ,  G01R31/02

    CPC classification number: G01R1/07307 ,  G01R1/0483 ,  G01R31/2831 ,  G01R31/2886 ,  H05K3/325 ,  H05K3/4007

    Abstract: An apparatus for testing unpackaged semiconductor dice having raised ball contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the ball contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

    Abstract translation: 公开了一种用于测试具有凸起的球接触位置的未包装半导体晶片的测试装置。 该装置使用临时互连晶片，该临时互连晶片适于与模具上的凸起的球接触位置建立电连接，而不会损坏球接触位置。 互连制造在诸如硅的衬底上，其中接触构件以与待测试的管芯上的球接触位置的尺寸和间距匹配的图案形成。 互连晶片上的接触构件形成为凹坑，凹槽或尖峰触点。 尖钉触点穿过形成在凸起接触位置上的氧化物层。 导电迹线设置在行和列中，并且终止于形成在基板中的凹坑的壁的内边缘。

    Methods for fabricating and filling conductive vias and conductive vias so formed
    38.
    发明申请
    Methods for fabricating and filling conductive vias and conductive vias so formed 有权
    制造和填充如此形成的导电通孔和导电通孔的方法

    公开(公告)号：US20070184654A1

    公开(公告)日：2007-08-09

    申请号：US11347153

    申请日：2006-02-03

    Applicant: Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    Inventor： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    IPC: H01L21/44

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

    Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

    Abstract translation: 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其他特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

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