公开(公告)号：US20050062168A1

公开(公告)日：2005-03-24

申请号：US10936503

申请日：2004-09-09

Applicant: Takeshi Sano ,  Yoshihiro Yoshida ,  Hideaki Ohkura ,  Hirofumi Kobayashi

Inventor： Takeshi Sano ,  Yoshihiro Yoshida ,  Hideaki Ohkura ,  Hirofumi Kobayashi

IPC: H01L21/60 ,  H01L23/485 ,  H05K1/18 ,  H05K3/32 ,  H05K3/36 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13369 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81855 ,  H01L2224/81885 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/351 ,  H05K3/321 ,  H05K2201/0248 ,  H05K2201/0272 ,  H05K2201/0379 ,  H05K2203/0425 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29344 ,  H01L2224/29339 ,  H01L2224/29369 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2929 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A disclosed bonded structure includes a first electric structure having a first electrode, a second electric structure having a second electrode, and a middle section for electrically and mechanically bonding the first electrode and the second electrode. The middle section consists of conductive adhesives, wherein fusion bonding of metal particles is provided to at least one of the first electrode and the second electrode. The metal particles are capable of fusion bonding at a temperature lower than a thermal hardening temperature of the conductive adhesives. The conductive adhesives contain conductive filler pieces that have a particle size at which fusion bonding does not take place at a temperature lower than the thermal hardening temperature of the conductive adhesives.

Abstract translation: 所公开的接合结构包括具有第一电极的第一电结构，具有第二电极的第二电结构和用于电和机械地结合第一电极和第二电极的中间部分。 中间部分由导电粘合剂组成，其中金属颗粒的熔融粘合提供给第一电极和第二电极中的至少一个。 金属颗粒能够在低于导电粘合剂的热硬化温度的温度下熔合。 导电性粘合剂含有导电性填料片，其导电性填充片具有在比导电性粘合剂的热硬化温度低的温度下不发生熔融粘结的粒径。

公开(公告)号：US20040094842A1

公开(公告)日：2004-05-20

申请号：US10715649

申请日：2003-11-18

Inventor： Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

IPC: H01L023/48

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00014

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract translation: 一种电结构和相关制造方法，用于减少将第一衬底的第一导体与第二衬底的第二导电体（例如，芯片耦合到芯片载体;芯片载体）的结构中的热诱导应变 到电路卡）。 第一导电体的熔点超过第二导电体的熔点。 第二导电体可以包括共晶铅锡合金，而第一导电体可以包括非共晶铅锡合金。 第一导电体的一部分被不可焊接和不导电的材料涂覆或体积地包围。 通过施加位于第一和第二导电体的熔点之间的温度，第一和第二导电体通过在第一导电体的未涂覆部分处的表面粘附机械和电连接。

公开(公告)号：US20040038598A1

公开(公告)日：2004-02-26

申请号：US10450527

申请日：2003-06-20

Inventor： Ernst Steiner ,  Dieter Stroh ,  Horst Dieterle

IPC: H01R009/22

CPC classification number: B29C65/082 ,  B23K20/10 ,  B23K20/106 ,  B23K2101/38 ,  B29C66/1122 ,  B29C66/43 ,  H01R4/021 ,  H01R12/59 ,  H01R43/0207 ,  H01R43/0228 ,  H01R43/0263 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2203/0195 ,  H05K2203/0285 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49194 ,  Y10T29/49208 ,  Y10T29/53217 ,  Y10T29/53243

Abstract: The invention relates to a method and device for connecting the electrical conductors which are surrounded by outer insulation and associated with overlapping flat conductors (47, 49) by means of a sonotrode (52) producing ultrasonic vibrations and a counter electrode associated therewith. The conductors which are to be connected are to be arranged on a surface (48) of a carrier (50) extending between the sonotrode and the counter electrode. The carrier can be embodied as a counter electrode.

Abstract translation: 本发明涉及一种用于连接电导体的方法和装置，所述电导体被外绝缘层包围，并通过产生超声波振动的超声波发生器（52）和与之相关联的反电极与重叠的扁平导体（47,49）相关联。 要连接的导体将被布置在延伸在超声焊丝和对电极之间的载体（50）的表面（48）上。 载体可以实现为对电极。

公开(公告)号：US20040026107A1

公开(公告)日：2004-02-12

申请号：US10216580

申请日：2002-08-08

Inventor： John L. Caldwell ,  William J. Casey

IPC: H01L023/02

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/171 ,  H01L2224/81011 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/381 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/09427 ,  H05K2203/048 ,  Y02P70/613 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49174 ,  Y10T29/4921 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A plurality of electrical interconnections may be formed in an electrical device including a first component having a plurality of contact pads and a second component having a plurality of contact pads. The two components are placed in a confronting spaced relationship such that each contact pad of the first component locationally corresponds to one of the contact pads of the second component. The contact pads of the second component are further arranged such that at least two of the contact pads are laterally offset relative to their locationally corresponding contact pads on the first component with one of the at least two contact pads being offset in a first direction while the other is offset in another direction. A mass of conductive material is disposed between each contact pad of the first component and its corresponding contact pad of the second component. The masses of conductive material may be formed into columnar members wherein the columnar members are skewed when formed between a pair of relatively offset contact pads.

Abstract translation: 可以在包括具有多个接触焊盘的第一部件和具有多个接触焊盘的第二部件的电气设备中形成多个电互连。 两个部件被放置成相对间隔开的关系，使得第一部件的每个接触垫定位地对应于第二部件的接触焊盘之一。 第二部件的接触垫还被布置成使得至少两个接触焊盘相对于第一部件上的位置对应的接触焊盘侧向偏移，其中至少两个接触焊盘中的一个接触焊盘之一沿第一方向偏移，而 另一个方向偏移。 导电材料的质量被布置在第一部件的每个接触焊盘和其对应的第二部件的接触焊盘之间。 导电材料的质量可以形成为柱状构件，其中当形成在一对相对偏移的接触垫之间时，柱状构件歪斜。

公开(公告)号：US20040011555A1

公开(公告)日：2004-01-22

申请号：US10199835

申请日：2002-07-22

Inventor： Tsung Chin Chiu

IPC: H05K001/03

CPC classification number: H05K3/4647 ,  H05K3/064 ,  H05K2201/0379 ,  H05K2201/09881

Abstract: A method for manufacturing a printed circuit board with stacked wires and a printed circuit board made by the method are disclosed. In the printed circuit board, each wire layers being formed by pretreatment, coating or laminating photoimageable resist, exposing, developing, etching wires on a substrate; coating an insulating layer on the circuit board; removing the insulating layer upon the wires so as to expose the wires; and then performing PTH process and plating copper for forming another wires. Thereby, line thickness of the printed circuit board is increased and the wires are stacked continuously.

Abstract translation: 公开了一种制造具有堆叠线的印刷电路板的方法和通过该方法制造的印刷电路板。 在印刷电路板中，每个线层通过预处理，涂覆或层压光致成像抗蚀剂，曝光，显影，蚀刻在基片上的线形成; 在电路板上涂覆绝缘层; 去除导线上的绝缘层以露出电线; 然后执行PTH工艺并镀铜以形成另一根导线。 因此，印刷电路板的线路厚度增加，并且电线被连续堆叠。

公开(公告)号：US20030121700A1

公开(公告)日：2003-07-03

申请号：US10239811

申请日：2002-11-13

Inventor： Walter Schmidt

IPC: H05K003/42

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K3/4084 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/0195 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

Abstract: The invention comprises a method for manufacturing electrical connecting elements or semifinished products. Microvias are formed in a dielectric substrate layer by piercing a substrate layer (1) through a first conducting layer (3), which essentially covers an entire side of the substrate. The perforation depth (d) is at least equal to the total thickness of the substrate and the first conducting layer. The conductor material of the first conducting layer (3) during the piercing step is deformed so that it partially covers the wall of the hole fabricated by the piercing process. The little remaining distance between the conductor material and the opposite side of the substrate layer can easily be bridged by plating the side of the first conducting layer with additional conductor material. In this way, a reliable via contact is formed.

Abstract translation: 本发明包括一种用于制造电连接元件或半成品的方法。 通过穿透基底层（1）穿过基本上覆盖基底的整个侧面的第一导电层（3），在电介质基底层中形成微孔。 穿孔深度（d）至少等于基底和第一导电层的总厚度。 在穿刺步骤期间，第一导电层（3）的导体材料变形，使得其部分地覆盖通过穿孔工艺制造的孔的壁。 通过用另外的导体材料电镀第一导电层的侧面，可以容易地桥接导体材料和基底层的相对侧之间的剩余距离。 以这种方式形成可靠的通孔接点。

公开(公告)号：US20030107054A1

公开(公告)日：2003-06-12

申请号：US10346744

申请日：2003-01-17

Inventor： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC: H01L031/0328

CPC classification number: H05K3/3436 ,  H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

公开(公告)号：US06533160B1

公开(公告)日：2003-03-18

申请号：US09830201

申请日：2001-04-23

Applicant: Francis Bourrieres ,  Clement Kaiser

Inventor： Francis Bourrieres ,  Clement Kaiser

IPC: B23K3100

CPC classification number: H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H05K3/3478 ,  H05K2201/0379 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/0557

Abstract: A device (14) for implementing a method for setting on a substrate (2) interconnecting balls or preforms (1) comprising the following phases: storing in bulk the preforms (1); seizing in ordered position the preforms (1) with an adapted gripping device (9); setting the preforms (1) on the substrate (2) with the gripping device (9). Said device (14) is charaterized in that it consists of at least a matrix for storing the preforms, said matrix comprising a floor capable of acting as stop for the preforms when the matrix is being filled thereby enabling the implementation of a method whereby the passage from bulk storage to ordered storage is performed in masked time. The device is useful for incorporating or replacing balls in substrates of electronic components.

Abstract translation: 一种用于实现用于设置在包括以下阶段的球或预成型件（1）的基底（2）上的方法的装置（14）：大量储存预成型件（1）; 通过适配的夹持装置（9）在预成型件（1）的有序位置抓住; 用夹持装置（9）将预成型件（1）设置在基板（2）上。 所述装置（14）的特征在于其至少包括用于储存预成型件的基体，所述基体包括当填充基质时能够用作预制件停止的地板，从而能够实施通过 从大容量存储到订购的存储器在掩蔽时间内执行。 该装置对于在电子部件的基板中并入或更换球是有用的。

公开(公告)号：US20030049886A1

公开(公告)日：2003-03-13

申请号：US10237640

申请日：2002-09-06

Inventor： Peter C. Salmon

IPC: H01L021/44 ,  H01L021/48

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括轨迹宽度为5微米或更小的柔性多层互连电路。 用于制造液晶显示器，LCD，面板的玻璃面板制造设备用于制造互连电路。 在具有中间剥离层的玻璃载体上形成聚合物基层。 金属和电介质的交替层形成在基底层上，并被图案化以在玻璃面板上产生多层互连电路阵列。 在互连电路上沉积一层聚合物，并在输入/输出（I / O）焊盘位置形成开口。 将焊膏沉积在开口中以形成填充有焊料的孔。 在切割玻璃载体以形成分离的互连电路之后，使用倒装芯片接合对IC芯片进行螺柱凸起并组装，其中部件上的螺柱凸起插入到互连电路上的对应的孔中。 对IC芯片进行测试和返工以形成测试电路组件。 描述了连接到测试仪和其他模块和电子系统的方法。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器实施例。

公开(公告)号：US06499214B2

公开(公告)日：2002-12-31

申请号：US09812449

申请日：2001-03-20

Applicant: Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

Inventor： Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

IPC: H05K320

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。