公开(公告)号：US20050170648A1

公开(公告)日：2005-08-04

申请号：US11056758

申请日：2005-02-11

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

公开(公告)号：US09960088B2

公开(公告)日：2018-05-01

申请号：US13290879

申请日：2011-11-07

Applicant: Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B24B49/10 ,  H01L21/66 ,  B24B37/013 ,  B24B7/22 ,  H01L23/31

CPC classification number: H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

公开(公告)号：US09443783B2

公开(公告)日：2016-09-13

申请号：US13619877

申请日：2012-09-14

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/03 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14144 ,  H01L2224/14154 ,  H01L2224/14164 ,  H01L2224/14181 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

Abstract translation: 提供了一种三维堆叠半导体器件的系统和方法。 在一个实施例中，将两个或更多个半导体管芯附着到载体并封装。 两个或更多个半导体管芯的连接被暴露，并且两个或更多个半导体管芯可以被薄化以在相对侧上形成连接。 然后可以将另外的半导体管芯置于偏移或悬垂位置中。

公开(公告)号：US08866301B2

公开(公告)日：2014-10-21

申请号：US12781960

申请日：2010-05-18

Applicant: Yung-Chi Lin ,  Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Yung-Chi Lin ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/29 ,  H01L21/48

CPC classification number: H01L21/4857 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

Abstract translation: 封装系统包括设置在插入器上的第一集成电路。 所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。 第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。 第一集成电路与第一互连结构电耦合。

公开(公告)号：US08500182B2

公开(公告)日：2013-08-06

申请号：US12818022

申请日：2010-06-17

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: B25J15/00

CPC classification number: H01L21/67346 ,  H01L21/6838 ,  H01L21/68785

Abstract: An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.

Abstract translation: 用于支撑晶片的装置包括基座和气体穿透层。 气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。 气体通道被直接设置在气体穿透层上方的晶片密封。 该装置还包括连接到气体通道的阀。

公开(公告)号：US08455995B2

公开(公告)日：2013-06-04

申请号：US12762085

申请日：2010-04-16

Applicant: Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/04

CPC classification number: H01L23/3121 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

Abstract translation: 一种器件包括具有顶表面和底表面的衬底的插入器。 多个穿通基板通孔（TSV）穿过基板。 多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于第一长度的第二长度的第二TSV和与第一水平尺寸不同的第二水平尺寸。 互连结构形成在衬底的顶表面上并电耦合到多个TSV。

公开(公告)号：US20130087951A1

公开(公告)日：2013-04-11

申请号：US13270957

申请日：2011-10-11

Applicant: Jing-Cheng Lin ,  Hsien-Wen Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Hsien-Wen Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H05B6/64 ,  B29C35/08

CPC classification number: B29C35/0805 ,  B29C2035/0855 ,  H01L21/565 ,  H05B6/6491 ,  H05B6/806

Abstract: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/48 ,  H01L21/6835 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US08361895B2

公开(公告)日：2013-01-29

申请号：US12211464

申请日：2008-09-16

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/22 ,  H01L21/38

CPC classification number: H01L29/66636 ,  H01L21/2254 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/49 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

Abstract translation: 提供半导体器件和制造方法。 基板上形成有栅叠层。 通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。 衬底可以在形成原子层之前被凹入，并且凹槽可以通过外延工艺填充。 可以重复沉积，退火和（如果使用）外延生长以实现所需的结。 源极/漏极区域也设置在栅极堆叠的相对侧上。

公开(公告)号：US20130001776A1

公开(公告)日：2013-01-03

申请号：US13170973

申请日：2011-06-28

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L23/485 ,  H01L21/28

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/214

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract translation: 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料，模塑料和金属支柱之上。 后钝化互连（PPI）延伸到聚合物层中。 焊球在PPI上方，并通过PPI电耦合到金属焊盘。