公开(公告)号：US09451693B2

公开(公告)日：2016-09-20

申请号：US13198756

申请日：2011-08-05

申请人： Rabindra N. Das ,  Voya R. Markovich ,  John M. Lauffer ,  Roy H. Magnuson ,  Konstantinos I. Papathomas ,  Benson Chan

发明人： Rabindra N. Das ,  Voya R. Markovich ,  John M. Lauffer ,  Roy H. Magnuson ,  Konstantinos I. Papathomas ,  Benson Chan

IPC分类号： H05K1/11 ,  H05K1/03

CPC分类号： H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

摘要翻译： 用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。 具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。 导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。

公开(公告)号：US07814649B2

公开(公告)日：2010-10-19

申请号：US11482945

申请日：2006-07-10

申请人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

发明人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4641 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.

摘要翻译： 一种制造电路化衬底的方法，该衬底包括沿着其至少一个导电层的侧边缘部分的多个邻接的开放段，这些开放段通过电介质材料的屏障隔开，其基本上填充开放段，例如在 层压工艺，其将基板的两个电介质层粘合到导电层。

公开(公告)号：US07800916B2

公开(公告)日：2010-09-21

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01R12/16

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US07381587B2

公开(公告)日：2008-06-03

申请号：US11324432

申请日：2006-01-04

申请人： Robert M. Japp ,  John M. Lauffer ,  Voya R. Markovich ,  William E. Wilson

发明人： Robert M. Japp ,  John M. Lauffer ,  Voya R. Markovich ,  William E. Wilson

IPC分类号： H01L21/00

CPC分类号： H05K3/4641 ,  H05K3/429 ,  H05K2203/068

摘要： A method of making a circuitized substrate and an electrical assembly utilizing same in which the substrate is comprised of at least two sub-composites in which the dielectric material of at least one of these sub-composites is heated during bonding (e.g., lamination) to the other sufficiently to cause the dielectric material to flow into and substantially fill openings in a conductive layer for the bonded structure. Conductive thru-holes are formed within the bonded structure to couple selected ones of the structure's conductive layers. Formation of an electrical assembly is possible by positioning one or more electrical components (e.g., semiconductor chips or chip carriers) on the final structure and electrically coupling these to the structure's external circuitry.

摘要翻译： 一种制造电路化基板的方法和使用其的电气组件，其中基板由至少两个亚复合材料构成，其中这些亚复合材料中的至少一个的介电材料在粘合（例如，层压）期间被加热到 另一个足以使电介质材料流入并基本上填充用于接合结构的导电层中的开口。 导电通孔形成在接合结构内，以耦合所选择的结构导电层。 通过将一个或多个电气部件（例如，半导体芯片或芯片载体）定位在最终结构上并将其电耦合到结构的外部电路，可以形成电组件。

公开(公告)号：US07377033B2

公开(公告)日：2008-05-27

申请号：US11641810

申请日：2006-12-20

申请人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

发明人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC分类号： H01K3/10

CPC分类号： H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

摘要： A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.

摘要翻译： 一种制造电路化衬底的方法，其包括多个邻接的开放段，其限定导电层内的相对边缘部分以隔离导电层的分离部分，使得该层可用于不同的功能，例如电力和地面 元件，在包括基板作为其一部分的产品（例如，电气组件）内。 还提供了代表其中可以使用衬底的产品之一的信息处理系统，例如主机计算机。

公开(公告)号：US20070275525A1

公开(公告)日：2007-11-29

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8242

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US07211289B2

公开(公告)日：2007-05-01

申请号：US10737974

申请日：2003-12-18

申请人： James M. Larnerd ,  John M. Lauffer ,  Voya R. Markovich ,  Kostas I. Papathomas

发明人： James M. Larnerd ,  John M. Lauffer ,  Voya R. Markovich ,  Kostas I. Papathomas

IPC分类号： B05D5/12 ,  B28B19/00 ,  B29B15/10

CPC分类号： H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

摘要： A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

摘要翻译： 一种制造印刷电路板的方法，其中导电通孔形成在板结构的两个电介质层内，以便连接指定的导电层。 一个孔连接两个相邻的层，另一个连接两个相邻的层，包括通过另一个孔连接的一个导电层。 也可以使用一个或多个孔连接所有三个导电层。 所得到的孔可以例如用金属电镀或导电或不导电的糊料填充。 在后者的情况下，也可以在浆料上方设置顶部覆盖导电层，例如在板的外表面上用作衬垫等。

公开(公告)号：US07157647B2

公开(公告)日：2007-01-02

申请号：US10882170

申请日：2004-07-02

申请人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

发明人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC分类号： H05K1/11

CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4641 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.

摘要翻译： 电路化衬底，其包括沿其至少一个导电层的侧边缘部分的多个邻接的开放段，这些开放段通过电介质材料的屏障隔离，所述阻挡层基本上填充开放段，例如在层压过程期间 将基板的两个电介质层粘合到导电层。 还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

公开(公告)号：US06830875B2

公开(公告)日：2004-12-14

申请号：US10266020

申请日：2002-10-07

申请人： Stephen J. Fuerniss ,  Gary Johansson ,  Ross W. Keesler ,  John M. Lauffer ,  Voya R. Markovich ,  Peter A. Moschak ,  David J. Russell ,  William E. Wilson

发明人： Stephen J. Fuerniss ,  Gary Johansson ,  Ross W. Keesler ,  John M. Lauffer ,  Voya R. Markovich ,  Peter A. Moschak ,  David J. Russell ,  William E. Wilson

IPC分类号： G03F700

CPC分类号： H05K3/0023 ,  H05K1/056 ,  H05K3/445 ,  H05K3/4641 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.

摘要翻译： 一种形成电子结构的方法。 提供是包括可光成像电介质（PID）材料的圆柱体积，围绕圆柱体积的PID材料的环形体积以及围绕环形体积的PID材料的剩余体积的层。 该层被光刻地暴露于辐射。 环形体积被辐射完全固化。 剩余体积由所述辐射的剩余体积部分固化。 该方法防止圆柱体积的固化，其中圆柱体积中的PID材料保持未固化。

公开(公告)号：US06750405B1

公开(公告)日：2004-06-15

申请号：US09690485

申请日：2000-10-17

申请人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

发明人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC分类号： H01R1204

CPC分类号： H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

摘要翻译： 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。