公开(公告)号：US20100213610A1

公开(公告)日：2010-08-26

申请号：US12775188

申请日：2010-05-06

申请人： Pandi Chelvam Marimuthu ,  Nathapong Suthiwongsunthorn ,  Kock Liang Heng

发明人： Pandi Chelvam Marimuthu ,  Nathapong Suthiwongsunthorn ,  Kock Liang Heng

IPC分类号： H01L23/498

CPC分类号： H01L23/3128 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16238 ,  H01L2224/73265 ,  H01L2224/81385 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/19041

摘要： A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

摘要翻译： 半导体器件具有形成在衬底的第一侧上的第一互连结构。 半导体管芯安装到第一互连结构。 密封剂沉积在半导体管芯和第一互连结构上用于结构支撑。 衬底的与衬底的第一侧相对的第二侧的一部分被去除以减小其厚度。 密封剂在稀化过程中保持基材的坚固性。 TSV通过衬底的第二侧形成到第一互连结构。 在TSV中形成第二互连结构。 TSV具有形成在衬底的第二侧上的第一绝缘层和形成在第一绝缘层上并进入TSV的第一导电层。 第二互连结构具有在远离TSV的区域中形成在第一导电层之上的第二导电层。

公开(公告)号：US20100133704A1

公开(公告)日：2010-06-03

申请号：US12325587

申请日：2008-12-01

申请人： Pandi Chelvam Marimuthu ,  Nathapong Suthiwongsunthorn ,  Il Kwon Shim ,  Kock Liang Heng

发明人： Pandi Chelvam Marimuthu ,  Nathapong Suthiwongsunthorn ,  Il Kwon Shim ,  Kock Liang Heng

IPC分类号： H01L23/52 ,  H01L21/00 ,  H01L23/48 ,  H01L23/28

CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/82039 ,  H01L2224/9222 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.

摘要翻译： 通过提供用于支撑半导体器件的载体来制造半导体器件。 第一半导体管芯安装到载体上。 第一半导体管芯具有接触焊盘。 第一个虚设裸片安装在载体上。 第一个虚设裸片具有穿硅通孔（TSV）。 使用晶片模制材料封装第一半导体管芯和第一个裸管管芯。 第一互连结构形成在第一半导体管芯和第一虚设裸片上。 第一互连结构连接到第一半导体管芯的接触焊盘和第一虚设管芯的TSV。 移除载体，在第一半导体管芯和第一虚设管芯上形成第二互连结构。 第二互连结构连接到第一虚设裸片的TSV。 半导体封装连接到第二互连结构。

公开(公告)号：US09355993B2

公开(公告)日：2016-05-31

申请号：US14791287

申请日：2015-07-03

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

公开(公告)号：US09076724B1

公开(公告)日：2015-07-07

申请号：US14038275

申请日：2013-09-26

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

摘要翻译： 一种集成电路系统的制造方法，其特征在于，包括具有通孔的模具，所述模具具有顶侧和底面; 安装在顶侧的通孔的顶部互连; 安装在底面的通孔的互连柱; 安装到所述互连柱的器件互连; 以及覆盖互连柱和器件互连的基底粘合剂。

公开(公告)号：US20120326297A1

公开(公告)日：2012-12-27

申请号：US13167566

申请日：2011-06-23

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L21/283 ,  H01L23/485

CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

摘要翻译： 半导体器件具有形成在半导体管芯上的第一导电层的半导体管芯。 第一绝缘层形成在半导体管芯上，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 互连结构形成在第二绝缘层的开口内的第一和第二导电层之上。 去除第二绝缘层。 互连结构可以是导电柱或导电垫。 凸起材料可以形成在导电柱上。 在导电柱或垫上方形成一层厚度小于1微米的保护涂层以减少氧化。 通过将导电柱或垫浸入含有锡或铟的浴中形成保护涂层。

公开(公告)号：US07936055B2

公开(公告)日：2011-05-03

申请号：US11466748

申请日：2006-08-23

申请人： Antonio B. Dimaano, Jr. ,  Pandi Chelvam Marimuthu

发明人： Antonio B. Dimaano, Jr. ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/495 ,  H01L21/44

CPC分类号： H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system is provided including forming a first external interconnect and a die paddle having a slot, forming an inner terminal from a peripheral region of the die paddle, connecting an integrated circuit die and the peripheral region for ground connection, and molding through the slot.

摘要翻译： 提供了一种集成电路封装系统，包括形成第一外部互连和具有槽的管芯，从管芯的外围区域形成内部端子，连接集成电路管芯和用于接地连接的外围区域，以及通过 插槽。

公开(公告)号：US07880293B2

公开(公告)日：2011-02-01

申请号：US12055171

申请日：2008-03-25

申请人： Byung Joon Han ,  Nathapong Suthiwongsunthorn ,  Pandi Chelvam Marimuthu ,  Kock Liang Heng

发明人： Byung Joon Han ,  Nathapong Suthiwongsunthorn ,  Pandi Chelvam Marimuthu ,  Kock Liang Heng

IPC分类号： H01L23/04

CPC分类号： H01L23/147 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/552 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/05599

摘要： A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.

摘要翻译： 半导体器件具有用于支撑器件的晶片和形成在晶片顶表面上的导电层。 载体晶片永久地接合在导电层上。 在晶片和载体晶片内形成互连结构。 所述互连结构包括形成在所述晶片中的暴露所述导电层的第一通孔，暴露所述导电层的所述载体晶片中形成的第二通孔，沉积在所述第一通孔上的第一金属层，所述第一金属层与所述导电层电接触 以及沉积在所述第二通孔上的第二金属层，所述第二金属层与所述导电层电接触。 第一和第二钝化层沉积在第一和第二金属层上。 第一钝化层或第二钝化层具有蚀刻部分以暴露第一金属层或第二金属层的一部分。

公开(公告)号：US20100140752A1

公开(公告)日：2010-06-10

申请号：US12332325

申请日：2008-12-10

申请人： Pandi Chelvam Marimuthu ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn

发明人： Pandi Chelvam Marimuthu ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn

IPC分类号： H01L29/40 ,  H01L21/44 ,  H01L23/538 ,  H01L29/41

CPC分类号： H01L23/481 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion.

摘要翻译： 半导体器件具有形成在衬底的顶表面上的第一导电层。 在衬底上形成第一绝缘层。 第一绝缘层形成在第一绝缘层上。 在第一导电层和第一介电层上形成第二导电层。 第二介电层形成在第二导电层上。 聚合物材料沉积在第二介电层和第二导电层上。 在聚合物材料和第二导电层上形成第三导电层。 第三导电层电连接到第二导电层。 在第三导电层上形成第一焊料凸块。 通过衬底的背面形成导电通孔。 导电通孔电连接到第一导电层。 聚合物材料具有低的热膨胀系数。

公开(公告)号：US07554179B2

公开(公告)日：2009-06-30

申请号：US11053564

申请日：2005-02-07

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey D. Punzalan ,  Pandi Chelvam Marimuthu

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey D. Punzalan ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/495 ,  H01L21/50 ,  H01L23/28 ,  H01L23/48 ,  H05K3/34

CPC分类号： H01L23/49568 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe having a heat spreader and a plurality of terminal leads around the periphery of the heat spreader is provided. The die pad is attached to the heat spreader, and the plurality of contact leads is attached to the plurality of terminal leads.

摘要翻译： 多引线框半导体封装和制造方法包括具有管芯焊盘和围绕管芯焊盘周边的多个接触引线的第一引线框架。 模具附接到管芯焊盘并电连接到多个接触引线。 提供了具有散热器的散热器引线框架和围绕散热器周边的多个端子引线。 芯片焊盘安装在散热器上，多个接触引线安装在多个端子引线上。

公开(公告)号：US07378300B2

公开(公告)日：2008-05-27

申请号：US11234528

申请日：2005-09-22

申请人： Pandi Chelvam Marimuthu ,  Il Kwon Shim

发明人： Pandi Chelvam Marimuthu ,  Il Kwon Shim

IPC分类号： H01L21/00

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.

摘要翻译： 提供了一种集成电路封装系统，包括形成引线框架结构，该引线框架结构具有主要位于引线框架结构内部的封装空间，并将管芯附接到引线框架结构内密封空间中的引线框架结构。 该系统还包括将管芯与引线框结构电连接并将密封剂注入密封空间以形成集成电路封装系统。