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41.发明申请Semiconductor Device and Method of Forming a Wafer Level Package with Bump Interconnection 有权半导体器件和形成具有凹凸互连的晶片级封装的方法公开(公告)号：US20100072618A1
公开(公告)日：2010-03-25
申请号：US12235000
申请日：2008-09-22
CPC分类号： H01L23/5389 , H01L21/565 , H01L21/6835 , H01L23/3128 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L25/105 , H01L25/50 , H01L2224/24226 , H01L2224/73267 , H01L2224/82005 , H01L2224/82031 , H01L2224/82039 , H01L2224/92244 , H01L2224/96 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor device is made by providing a metal substrate for supporting the semiconductor device. Solder bumps are connected to the substrate. In one embodiment, a conductive material is deposited over the substrate and is reflowed to form the solder bumps. A semiconductor die is mounted to the substrate using a die attach adhesive. The semiconductor die has a plurality of contact pads formed over a surface of the semiconductor die. An encapsulant material is deposited over the solder bumps and the semiconductor die. The encapsulant is etched to expose the contact pads of the semiconductor die. A first redistribution layer (RDL) is formed over the encapsulant to connect each contact pad of the semiconductor die to one of the solder bumps. The substrate is removed to expose the die attach adhesive and a bottom surface of the solder bumps.
摘要翻译： 通过设置用于支撑半导体器件的金属基板来制造半导体器件。 焊接凸块连接到基板。 在一个实施例中，导电材料沉积在衬底上并被回流以形成焊料凸块。 使用芯片附着粘合剂将半导体管芯安装到基板上。 半导体管芯具有形成在半导体管芯的表面上的多个接触焊盘。 在焊料凸块和半导体管芯上沉积密封材料。 蚀刻密封剂以暴露半导体管芯的接触焊盘。 第一再分配层（RDL）形成在密封剂上方以将半导体管芯的每个接触焊盘连接到焊料凸块之一。 去除衬底以暴露芯片附着粘合剂和焊料凸块的底表面。
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公开(公告)号：US20090166821A1
公开(公告)日：2009-07-02
申请号：US12398806
申请日：2009-03-05
IPC分类号： H01L23/495
CPC分类号： H01L23/49551 , H01L23/3121 , H01L23/49811 , H01L24/48 , H01L25/03 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1029 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.
摘要翻译： 半导体封装包括引线框架。 第一引线指具有下部，从下部垂直向上延伸的连接部分和基本平坦的顶部。 顶部形成顶部端子引线结构。 第二引线指电连接到第一引线指。 第二引线指的一部分形成底部端子引线结构。 第二引线指的一部分对应于半导体封装的底表面。 基本平坦的顶部的表面对应于半导体封装的顶表面。
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公开(公告)号：US06833287B1
公开(公告)日：2004-12-21
申请号：US10463007
申请日：2003-06-16
IPC分类号： H01L2144
CPC分类号： H01L25/50 , H01L23/3128 , H01L24/45 , H01L25/0657 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4912 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
摘要翻译： 提供了具有堆叠模具的半导体封装和组装方法。 第一裸片附着在基片上。 保护层在其中心区域上放置在第一管芯上。 第一管芯与衬底电连接。 将中间粘合剂层施加在保护层上。 第二模具附接到中间粘合剂层并电连接到基底。
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44.发明授权Semiconductor device and method of forming wafer level ground plane and power ring 有权半导体器件及其形成晶圆级接地面和电源环的方法公开(公告)号：US09390991B2
公开(公告)日：2016-07-12
申请号：US13346415
申请日：2012-01-09
IPC分类号： H01L23/31 , H01L23/58 , H01L23/528 , H01L23/00 , H01L21/683 , H01L21/56
CPC分类号： H01L24/02 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3157 , H01L23/3171 , H01L23/3185 , H01L23/528 , H01L23/5286 , H01L23/585 , H01L24/05 , H01L24/13 , H01L24/18 , H01L24/19 , H01L24/82 , H01L24/96 , H01L2224/02315 , H01L2224/02371 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05024 , H01L2224/12105 , H01L2224/13026 , H01L2224/18 , H01L2224/32145 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
摘要翻译： 半导体管芯具有在其有源表面上形成的有源电路。 接触焊盘形成在半导体管芯的有源表面上并耦合到有源电路。 在半导体管芯的周围形成管芯延伸区域。 导电THV形成在芯片延伸区域中。 晶片级导电平面或环形成在有源表面的中心区域上。 导电平面或环连接到第一接触焊盘以向有源电路提供第一电源电位，并且电连接到第一导电THV。 导电环部分地围绕导电平面或环的周边形成并且连接到第二接触焊盘，以向有源电路提供第二电源电位。 导电环电连接到第二THV。
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45.发明授权Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die 有权具有嵌入式半导体芯片的预制散热器框架的半导体装置和方法公开(公告)号：US08518749B2
公开(公告)日：2013-08-27
申请号：US12489177
申请日：2009-06-22
CPC分类号： H01L23/562 , H01L21/4871 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L23/34 , H01L23/3672 , H01L23/4334 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/95 , H01L2224/0401 , H01L2224/04105 , H01L2224/1134 , H01L2224/13022 , H01L2224/16 , H01L2224/16235 , H01L2224/20 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
摘要翻译： 通过将预制散热器框架安装在临时衬底上来制造半导体器件。 散热器框架包括平板上的垂直体。 将半导体管芯安装到散热器框架上用于散热。 在垂直体和半导体管芯周围沉积密封剂，同时留下露出的半导体管芯上的接触焊盘。 可以使用晶片级直接/顶栅模制工艺或晶片级膜辅助模制工艺来沉积密封剂。 在半导体管芯上形成互连结构。 互连结构包括形成在半导体管芯上的第一导电层，形成在第一导电层上的绝缘层，以及形成在第一导电层和绝缘层上的第二导电层。 去除临时衬底，将切割带施加到散热器框架，并且半导体管芯被切割。
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46.发明申请Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected Through Conductive Vias Formed in Encapsulant Around Die 有权半导体器件和形成包含堆叠半导体晶片的EWLB封装的方法通过在模具周围的密封剂中形成的导电通孔电连接公开(公告)号：US20120299191A1
公开(公告)日：2012-11-29
申请号：US13116328
申请日：2011-05-26
申请人： Zigmund R. Camacho
发明人： Zigmund R. Camacho
CPC分类号： H01L21/56 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/24011 , H01L2224/24105 , H01L2224/24146 , H01L2224/245 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/821 , H01L2224/92244 , H01L2224/94 , H01L2224/96 , H01L2225/1035 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2224/82 , H01L2924/00014 , H01L2924/0105 , H01L2924/01028 , H01L2924/01022 , H01L2224/19 , H01L2924/00 , H01L2224/03
摘要： A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.
摘要翻译： 半导体器件具有第一半导体管芯和围绕第一半导体管芯沉积的第一密封剂。 在第一半导体管芯和第一密封剂上形成第一绝缘层。 第一导电层形成在第一绝缘层之上，并电连接到第一半导体管芯的接触焊盘。 第二半导体管芯安装到第一绝缘层和第一导电层。 第二密封剂沉积在第二半导体管芯周围。 在第二半导体管芯和第二密封剂上形成第二绝缘层。 第二导电层形成在第二绝缘层之上并电连接到第二半导体管芯的接触焊盘。 多个导电通孔连续地穿过电连接到第一和第二导电层的第一和第二半导体管芯的覆盖区之外的第一和第二密封剂形成。
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47.发明授权Semiconductor device and method of forming a conductive via-in-via structure 有权半导体器件和形成导电通孔在通孔结构的方法公开(公告)号：US08283250B2
公开(公告)日：2012-10-09
申请号：US12332318
申请日：2008-12-10
IPC分类号： H01L21/20
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/04042 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/16225 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.
摘要翻译： 半导体器件由包含由周边区域分离的半导体管芯的半导体晶片制成。 在周边区域或通过器件的有源区域形成导电通孔结构，以提供额外的拉伸强度。 导电通孔结构包括由绝缘材料隔开的内部导电通孔和外部导电通孔。 中间导电通孔可以形成在内导电通孔和外导电通孔之间。 内部导电通孔具有与半导体器件的第一表面相邻的第一横截面区域和与半导体器件的第二表面相邻的第二横截面区域。 外导电通孔具有与半导体器件的第一表面相邻的第一横截面区域和与半导体器件的第二表面相邻的第二横截面区域。 第一截面积与第二横截面积不同。
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公开(公告)号：US20110204512A1
公开(公告)日：2011-08-25
申请号：US13101657
申请日：2011-05-05
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L24/85 , H01L21/6835 , H01L24/24 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/82 , H01L24/83 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/13008 , H01L2224/16 , H01L2224/24227 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48464 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/82001 , H01L2224/83191 , H01L2224/83856 , H01L2224/85001 , H01L2224/85051 , H01L2224/85986 , H01L2224/92244 , H01L2225/06506 , H01L2225/06527 , H01L2225/06582 , H01L2225/06586 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.
摘要翻译： 半导体封装包括具有模腔和凸起腔的载体条。 半导体管芯安装在载体条的模腔中。 在一个实施例中，使用管芯附着粘合剂安装半导体管芯。 在一个实施例中，第一半导体管芯的顶表面与载体带的靠近模腔的顶表面近似共面。 金属层设置在载体带上方以形成封装凸块和在封装凸块与第一半导体管芯的接触焊盘之间的电镀互连。 在第一半导体管芯和模腔的表面之间的模腔中设置底部填充材料。 钝化层设置在第一半导体管芯上并且暴露第一半导体管芯的接触焊盘。 密封剂设置在载体条上。
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公开(公告)号：US08502376B2
公开(公告)日：2013-08-06
申请号：US13101657
申请日：2011-05-05
IPC分类号： H01L23/498
CPC分类号： H01L24/85 , H01L21/6835 , H01L24/24 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/82 , H01L24/83 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/13008 , H01L2224/16 , H01L2224/24227 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48464 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/82001 , H01L2224/83191 , H01L2224/83856 , H01L2224/85001 , H01L2224/85051 , H01L2224/85986 , H01L2224/92244 , H01L2225/06506 , H01L2225/06527 , H01L2225/06582 , H01L2225/06586 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.
摘要翻译： 半导体封装包括具有模腔和凸起腔的载体条。 半导体管芯安装在载体条的模腔中。 在一个实施例中，使用管芯附着粘合剂安装半导体管芯。 在一个实施例中，第一半导体管芯的顶表面与载体带的靠近模腔的顶表面近似共面。 金属层设置在载体带上方以形成封装凸块和在封装凸块与第一半导体管芯的接触焊盘之间的电镀互连。 在第一半导体管芯和模腔的表面之间的模腔中设置底部填充材料。 钝化层设置在第一半导体管芯上并且暴露第一半导体管芯的接触焊盘。 密封剂设置在载体条上。
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50.发明申请Semiconductor Device and Method of Forming a Reconfigured Stackable Wafer Level Package with Vertical Interconnect 有权半导体器件和形成具有垂直互连的重新配置的可堆叠晶片级封装的方法公开(公告)号：US20130069222A1
公开(公告)日：2013-03-21
申请号：US13234535
申请日：2011-09-16
申请人： Zigmund R. Camacho
发明人： Zigmund R. Camacho
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/486 , H01L21/561 , H01L21/568 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2224/03
摘要： A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.
摘要翻译： 半导体器件具有带有半导体管芯安装区域的载体。 多个导电柱形成在半导体管芯安装区域的周边和载体中。 移除载体的第一部分以暴露多个导电柱的第一部分，使得多个导电柱的第二部分嵌入载体的第二部分中。 第一半导体管芯安装到半导体管芯安装区域和多个导电柱的第一部分之间。 围绕第一半导体管芯并围绕多个导电柱的第一部分沉积第一密封剂。 移除载体的第二部分以暴露多个导电柱的第二部分。 在多个导电柱和第一半导体管芯之上形成互连结构。
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