-
公开(公告)号：US06833287B1
公开(公告)日：2004-12-21
申请号：US10463007
申请日：2003-06-16
IPC分类号： H01L2144
CPC分类号： H01L25/50 , H01L23/3128 , H01L24/45 , H01L25/0657 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4912 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
摘要翻译： 提供了具有堆叠模具的半导体封装和组装方法。 第一裸片附着在基片上。 保护层在其中心区域上放置在第一管芯上。 第一管芯与衬底电连接。 将中间粘合剂层施加在保护层上。 第二模具附接到中间粘合剂层并电连接到基底。
-
2.发明授权Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection 有权半导体器件和形成具有顶部和底部焊料凸块互连的晶片级封装的方法公开(公告)号：US08546189B2
公开(公告)日：2013-10-01
申请号：US12410213
申请日：2009-03-24
申请人： Zigmund R. Camacho , Lionel Chien Hui Tay , Henry D. Bathan , Jeffrey D. Punzalan , Dioscoro A. Merilo
发明人： Zigmund R. Camacho , Lionel Chien Hui Tay , Henry D. Bathan , Jeffrey D. Punzalan , Dioscoro A. Merilo
CPC分类号： H01L23/49811 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/11 , H01L24/24 , H01L24/48 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/211 , H01L2224/24145 , H01L2224/24998 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2224/73267 , H01L2224/82007 , H01L2224/83005 , H01L2225/06524 , H01L2225/06527 , H01L2225/06568 , H01L2225/06582 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/15747 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.
摘要翻译： 通过在铜载体上形成焊料凸块制成半导体器件。 在铜载体中形成焊接捕获压痕以接收焊料凸块。 使用芯片附着粘合剂将半导体管芯安装到铜载体上。 半导体管芯具有形成在其有源表面上的接触焊盘。 封装剂沉积在铜载体，焊料凸块和半导体芯片上。 去除一部分密封剂以暴露焊料凸块和接触垫。 在密封剂上形成导电层以连接焊料凸块和接触焊盘。 导电层作为再分配层工作，以将电信号从焊料凸块路由到接触焊盘。 铜载体被去除。 在导电层和密封剂之上形成绝缘层。 多个半导体器件可以堆叠并通过焊料凸块电连接。
-
3.发明授权Semiconductor package and method of forming similar structure for top and bottom bonding pads 有权半导体封装和形成顶部和底部焊盘的类似结构的方法公开(公告)号：US08039302B2
公开(公告)日：2011-10-18
申请号：US11952502
申请日：2007-12-07
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L24/16 , H01L24/18 , H01L24/19 , H01L24/81 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05569 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/12105 , H01L2224/16225 , H01L2224/18 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2225/06524 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19107 , H01L2924/30105 , H01L2924/0665 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in electrical contact with the conductive via and the first semiconductor die. A second RDL is formed on a second surface of the substrate opposite the first surface of the substrate die in electrical contact with the conductive via. A second semiconductor die can be mounted on the substrate and electrically connected to the second RDL. Bonding pads are formed over the first and second surfaces of the substrate in electrical contact with the first and second RDLs, respectively. The bonding pads on opposite surfaces of the substrate are aligned. Solder bumps or bond wires can be formed on the bonding pads. The semiconductor packages can be stacked and electrically connected through the aligned bonding pads.
摘要翻译： 半导体封装具有安装在基板上的第一半导体管芯。 通过衬底形成导电通孔。 第一RDL形成在与导电通孔和第一半导体管芯电接触的基板的第一表面上。 第二RDL形成在与导电通孔电接触的与衬底管芯的第一表面相对的衬底的第二表面上。 第二半导体管芯可以安装在基板上并电连接到第二RDL。 接合焊盘分别形成在基板的第一和第二表面上，与第一和第二RDL电接触。 对准衬底的相对表面上的接合焊盘。 焊接凸块或接合线可以形成在焊盘上。 半导体封装可以通过对准的焊盘层叠并电连接。
-
公开(公告)号：US20090243064A1
公开(公告)日：2009-10-01
申请号：US12060115
申请日：2008-03-31
CPC分类号： H01L23/3121 , H01L23/3128 , H01L23/4334 , H01L23/4952 , H01L23/49548 , H01L23/49575 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/91 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/49109 , H01L2224/4911 , H01L2224/49111 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/83 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/1515 , H01L2924/15311 , H01L2924/15724 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/19103 , H01L2924/19107 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/4826
摘要： A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices.
摘要翻译： 制造半导体封装的方法包括提供具有窗口的基板。 衬底可以包括具有半蚀刻引线的引线框架。 使用粘合剂将第一和第二半导体器件安装到窗口两侧的基板的顶表面。 使用粘合剂将第三半导体器件安装到第一和第二半导体器件。 第三半导体器件设置在衬底的窗口之上。 在第三半导体器件和形成在衬底的与衬底的顶表面相对的底表面上的接触焊盘之间形成引线接合或其它电互连。 引线键或其他电互连通过基板的窗口。 密封剂沉积在第一，第二和第三半导体器件上。
-
5.发明授权Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die 有权用基极引线和嵌入式半导体芯片形成晶圆级多行蚀刻引线框的半导体器件和方法公开(公告)号：US08993376B2
公开(公告)日：2015-03-31
申请号：US13284811
申请日：2011-10-28
IPC分类号： H01L21/00 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/495 , H01L21/48 , H01L25/16
CPC分类号： H01L24/29 , H01L21/4832 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/83805 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/81805
摘要： A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
摘要翻译： 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面中形成有在空腔之间的多个空腔和基底引线。 第一组基线可以具有与第二组基线不同的高度或相似的高度。 可以在第二组基线上形成凹形捕获垫。 或者，可以在基底基板和安装到开口的半导体管芯上形成多个开口。 半导体管芯安装在第一组基极引线之间和第二组基极引线之间。 密封剂沉积在管芯和基底衬底上。 去除基底基板的第二表面的一部分以分离基底引线。 在密封剂和基底引线上形成互连结构。
-
6.发明授权Semiconductor device and method of forming a protective layer on a backside of the wafer 有权在晶片的背面形成保护层的半导体装置和方法公开(公告)号：US08802505B2
公开(公告)日：2014-08-12
申请号：US12242011
申请日：2008-09-30
IPC分类号： H01L21/44
CPC分类号： H01L23/3107 , H01L23/562 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16245 , H01L2224/73253 , H01L2924/00014 , H01L2924/01322 , H01L2924/12044 , H01L2924/13091 , H01L2924/1433 , H01L2924/18161 , H01L2924/19041 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device is made by forming solder bumps on a first side of a semiconductor wafer. A protective layer is formed on a second side of the semiconductor wafer opposite the first side. The protective layer can be adhesive paste, laminated film, spin-coated resin, epoxy based elastomer, organic rubbery material, polystyrene, polyethylene terephthalate, or other polymer material. The semiconductor wafer is singulated into semiconductor die. The semiconductor die is mounted to a carrier. A molding compound is formed around the semiconductor die. The protective layer provides stress relief for the semiconductor die. The protective layer is removed from the semiconductor die. The protective layer can provide a thermal dissipation, in which case it is made with metal or polymer-based material with a filler such as alumina, zinc oxide, silicon dioxide, silver, aluminum, and aluminum nitride.
摘要翻译： 通过在半导体晶片的第一面上形成焊料凸块来制造半导体器件。 在半导体晶片的与第一侧相反的第二侧上形成保护层。 保护层可以是粘合剂糊剂，层压膜，旋涂树脂，环氧基弹性体，有机橡胶材料，聚苯乙烯，聚对苯二甲酸乙二醇酯或其它聚合物材料。 半导体晶片被分成半导体晶片。 半导体管芯安装在载体上。 在半导体管芯周围形成模塑料。 保护层为半导体管芯提供了应力消除。 从半导体管芯移除保护层。 保护层可以提供热耗散，在这种情况下，其由具有诸如氧化铝，氧化锌，二氧化硅，银，铝和氮化铝的填料的金属或聚合物基材料制成。
-
7.发明申请Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps 有权半导体器件和形成EWLB封装的隔离导电层在封装冲击波上的方法公开(公告)号：US20120326337A1
公开(公告)日：2012-12-27
申请号：US13167133
申请日：2011-06-23
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/19 , H01L2224/96 , H01L2224/97 , H01L2225/1035 , H01L2924/00 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 凹槽部分地通过载体在芯片附着区域外部形成。 第一导电层保形地施加在载体的表面上并进入凹部。 将半导体管芯安装到载体的管芯附着区域。 封装剂沉积在载体和半导体管芯上。 密封剂延伸到第一导电层上的凹槽中以形成密封剂凸块。 去除载体以将第一导电层暴露在密封剂凸块之上。 在半导体管芯上形成第一绝缘层，具有开口以露出半导体管芯的接触焊盘。 在第一导电层和半导体管芯上的接触焊盘之间形成第二导电层。 在第二导电层和半导体管芯上形成第二绝缘层。
-
8.发明申请Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package 审中-公开半导体器件和形成晶圆级多行蚀刻引线封装的方法公开(公告)号：US20120273927A1
公开(公告)日：2012-11-01
申请号：US13543637
申请日：2012-07-06
IPC分类号： H01L23/552
CPC分类号： H01L21/56 , H01L23/28 , H01L25/11 , H01L2224/04105 , H01L2224/12105 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48229 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/13091 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
摘要翻译： 半导体器件具有具有第一和第二相对表面的基底载体。 基底托架的第一表面被蚀刻以形成在第一和第二表面之间延伸的空腔之间的多个空腔和多排基底引线。 第二导电层形成在基底载体的第二表面上。 半导体管芯安装在基座的空腔内。 第一绝缘层形成在基体载体的模具和第一表面上并进入空腔中。 在第一绝缘层和基底载体的第一表面上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 去除基底载体的第二表面的一部分以露出第一绝缘层并电绝缘基极。
-
9.发明申请Optical Semiconductor Device having Pre-Molded Leadframe with Window and Method Therefor 有权具有带窗口的预成型引线框的光半导体器件及其方法公开(公告)号：US20120168806A1
公开(公告)日：2012-07-05
申请号：US13419242
申请日：2012-03-13
IPC分类号： H01L31/18 , H01L31/0232
CPC分类号： H01L31/0203 , H01L21/563 , H01L23/3121 , H01L24/32 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15151 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
摘要翻译： 通过提供具有光学活性区域的半导体管芯制造半导体器件，提供具有多个接触焊盘的引线框架或预成型层叠基板和设置在接触焊盘之间的透光材料，将半导体管芯附接到引线框架 光学活性区域与透光材料对准以提供到光学有效区域的光传输路径，并且在半导体管芯和引线框架之间设置底部填充材料。 透光材料包括用于防止底部填充材料阻挡光传输路径的升高区域。 升高区域包括围绕光传输路径的堤坝，粘合环，或者光传输路径本身可以是高架区域。 可以在大坝上设置粘合环。 填充材料可以设置在透光材料和接触垫之间。
-
10.发明申请Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect 有权半导体器件和形成用于垂直电互连的半导体芯片和TSV基板的引线框架插入件的方法公开(公告)号：US20120061814A1
公开(公告)日：2012-03-15
申请号：US12882110
申请日：2010-09-14
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/495 , H01L21/4832 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/16225 , H01L2224/29144 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49113 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/831 , H01L2225/06517 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/1579 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H05K2203/0384 , H01L2924/01014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
摘要翻译： 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。
-
-
-
-
-
-
-
-
-
搜索结果
93 条记录 (耗时 0.029 秒)
