公开(公告)号：US20170092747A1

公开(公告)日：2017-03-30

申请号：US15280370

申请日：2016-09-29

申请人： Sumitomo Electric Industries, Ltd.

发明人： Ken Nakata

IPC分类号： H01L29/66 ,  H01L29/24 ,  H01L29/267 ,  H01L29/227 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/778 ,  H01L21/306 ,  H01L21/467 ,  H01L29/22 ,  H01L29/20

CPC分类号： H01L29/66969 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/30621 ,  H01L21/465 ,  H01L21/467 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/22 ,  H01L29/227 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7786

摘要： A HEMT made of nitride semiconductor materials and a process of forming the same are disclosed, where the HEMT has n-type regions beneath the source and drain electrodes with remarkably increased carrier concentration. The HEMT provides the n-type regions made of at least one of epitaxially grown ZnO layer and MgZnO layer each doped with at least aluminum and gallium with density higher than 1×1020 cm−3. The process of forming the HEMT includes steps of forming recesses by dry-etching, epitaxially growing n-type layer, removing surplus n-type layer except within the recesses by dry-etching using hydrocarbon, and forming the electrodes on the n-type layer.

公开(公告)号：US09595435B2

公开(公告)日：2017-03-14

申请号：US14055970

申请日：2013-10-17

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Masashi Tsubuku ,  Ryosuke Watanabe ,  Noritaka Ishihara ,  Masashi Oota

IPC分类号： H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L21/02422 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78693

摘要： To form an oxide semiconductor film with a low density of localized levels. To improve electric characteristics of a semiconductor device including the oxide semiconductor. After oxygen is added to an oxide film containing In or Ga in contact with an oxide semiconductor film functioning as a channel, heat treatment is performed to make oxygen in the oxide film containing In or Ga transfer to the oxide semiconductor film functioning as a channel, so that the amount of oxygen vacancies in the oxide semiconductor film is reduced. Further, an oxide film containing In or Ga is formed, oxygen is added to the oxide film, an oxide semiconductor film is formed over the oxide film, and then heat treatment is performed.

摘要翻译： 形成具有低密度局部化水平的氧化物半导体膜。 为了改善包括氧化物半导体的半导体器件的电特性。 在与用作沟道的氧化物半导体膜接触的含有In或Ga的氧化物膜上加氧后，进行热处理，使含有In或Ga的氧化物膜中的氧转移到作为通道发挥作用的氧化物半导体膜， 使得氧化物半导体膜中的氧空位量减少。 此外，形成含有In或Ga的氧化物膜，在氧化膜上添加氧，在氧化膜上形成氧化物半导体膜，然后进行热处理。

公开(公告)号：US20170069785A1

公开(公告)日：2017-03-09

申请号：US15183869

申请日：2016-06-16

申请人： Samsung Electronics Co., Ltd.

发明人： Young Jo TAK ,  Sam Mook KANG ,  Mi Hyun KIM ,  Jun Youn KIM ,  Young Soo PARK ,  Misaichi TAKEUCHI

IPC分类号： H01L33/00 ,  H01L21/02 ,  H01L21/78 ,  H01L21/683 ,  H01L21/306

CPC分类号： H01L33/0075 ,  H01L21/02005 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7806 ,  H01L33/0066 ,  H01L33/0079

摘要： A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.

摘要翻译： 制造半导体衬底的方法可以包括在生长衬底上形成第一半导体层，在第一半导体层上形成第二半导体层，在第一半导体层中形成多个空隙，通过去除第一半导体层的部分 在所述第二半导体层中由多个沟槽暴露，在所述第二半导体层上形成第三半导体层并覆盖所述多个沟槽，以及从所述生长衬底分离所述第二和第三半导体层。 在第一半导体层上。 第三半导体层从第二半导体层生长并在第二半导体层上方延伸。

公开(公告)号：US20170069716A1

公开(公告)日：2017-03-09

申请号：US14847260

申请日：2015-09-08

申请人： M/A-COM Technology Solutions Holdings, Inc.

发明人： John Claassen Roberts ,  Kevin J. Linthicum

IPC分类号： H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/36

CPC分类号： H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/0623 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/41758 ,  H01L29/7783

摘要： III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

摘要翻译： 这里通常描述III族氮化物材料，包括包含III族氮化物材料区域和含硅衬底的材料结构。 某些实施例涉及氮化镓材料和包含氮化镓材料区域和含硅衬底的材料结构。

公开(公告)号：US20170062215A1

公开(公告)日：2017-03-02

申请号：US15350071

申请日：2016-11-13

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Alexander Reznicek

IPC分类号： H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/20 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/2258 ,  H01L21/26513 ,  H01L21/3228 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8252 ,  H01L21/8256 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66446 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

摘要翻译： 包括III-V鳍结构和硅基源极/漏极区的FinFET器件形成在半导体衬底上。 硅扩散到III-V鳍结构中以形成n型结。 通过形成邻接源极/漏极区的p-n结并且在沟道区下方隔离III-V鳍结构来解决通过衬底的漏电。

公开(公告)号：US09583608B2

公开(公告)日：2017-02-28

申请号：US14418589

申请日：2013-05-24

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Yasuhiro Yamada ,  Yoshiharu Anda ,  Asamira Suzuki

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L21/285 ,  H01L29/205 ,  H01L29/417 ,  H01L29/49 ,  H01L29/267 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L21/02 ,  H01L23/00

CPC分类号： H01L29/7787 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02565 ,  H01L21/02579 ,  H01L21/28556 ,  H01L23/564 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4966 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.

摘要翻译： 本发明的氮化物半导体器件具有源电极侧绝缘体保护膜层，其设置在第二氮化物半导体层上的源电极和漏电极之间，并且至少部分地覆盖源电极，漏电极侧 绝缘体保护膜层，与源电极侧绝缘体保护膜层分离设置，并形成为至少部分地覆盖漏极电极;以及栅极层，其与源极侧绝缘体保护膜之间的第二氮化物半导体层接触形成 层和漏电极侧绝缘体保护膜层，由p型金属氧化物半导体构成，栅极层具有穿过源电极侧绝缘体保护膜层和第二氮化物半导体层的与第二氮化物半导体层相反的区域 漏电极侧绝缘体保护膜层和与第二氮化物半导体接触的区域 ctor层。

公开(公告)号：US09583577B2

公开(公告)日：2017-02-28

申请号：US14840732

申请日：2015-08-31

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Chisato Furukawa ,  Masaaki Ogawa ,  Takako Motai ,  Wakana Nishiwaki

IPC分类号： H01L29/32 ,  H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/20

CPC分类号： H01L29/32 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02647 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a third nitride semiconductor layer on the second nitride semiconductor layer, an electrode on the third nitride semiconductor layer, and an insulating layer under the electrode and between the first nitride semiconductor layer and the second nitride semiconductor layer.

摘要翻译： 半导体器件包括衬底，衬底上的第一氮化物半导体层，第一氮化物半导体层上的第二氮化物半导体层，第二氮化物半导体层上的第三氮化物半导体层，第三氮化物半导体层上的电极，以及 绝缘层，位于第一氮化物半导体层和第二氮化物半导体层之间。

公开(公告)号：US20170047424A1

公开(公告)日：2017-02-16

申请号：US15194728

申请日：2016-06-28

申请人： International Business Machines Corporation

发明人： Sanghoon Lee ,  Effendi Leobandung ,  Renee Mo ,  Brent A. Wacaser

IPC分类号： H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L29/66522 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/26546 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30612 ,  H01L21/30617 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/7624 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

摘要： In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

公开(公告)号：US09553250B2

公开(公告)日：2017-01-24

申请号：US15031559

申请日：2014-10-01

申请人： DENSO CORPORATION

发明人： Norio Gouko ,  Atusi Sakaida ,  Toshihisa Taniguchi ,  Yoshihiko Shiraishi ,  Keiji Okamoto

IPC分类号： H01L21/48 ,  H01L35/34 ,  H01L35/04 ,  H01L21/02

CPC分类号： H01L35/34 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/486 ,  H01L35/04 ,  H01L35/16 ,  H01L35/32

摘要： An insulating substrate to which intermediate portions or conductive pastes constituting the intermediate portions are disposed, a front surface protective member to which front surface patterns are formed, and a back surface protective member to which back surface patterns are formed are prepared. A laminated body, to which first end portions or conductive pastes constituting the first end portions are disposed between the intermediate portions or the conductive pastes constituting the intermediate portions and the front surface patterns, and second end portions or conductive pastes constituting the second end portions are disposed between the intermediate portions or the conductive pastes constituting the intermediate portions and the back surface patterns, is constituted. Then, thermoelectric conversion elements are formed by integrating the laminated body.

摘要翻译： 制成构成中间部分的中间部分或导电浆料的绝缘基底，形成前表面图案的前表面保护部件和形成背面图案的背面保护部件。 层叠体，构成第一端部的第一端部或导电性糊料配置在构成中间部的中间部或导电性糊料和前面图案之间，构成第二端部的第二端部或导电性糊料 设置在构成中间部分的中间部分或导电膏体和背面图案之间。 然后，通过使层叠体一体化形成热电转换元件。

公开(公告)号：US09553181B2

公开(公告)日：2017-01-24

申请号：US14727389

申请日：2015-06-01

申请人： Toshiba Corporation

发明人： Long Yang

IPC分类号： H01L21/338 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02

CPC分类号： H01L29/778 ,  H01L21/02271 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/2006 ,  H01L29/205 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786

摘要： The present disclosure presents a novel structure for a dielectric material for use with Group III-V material systems and a method of fabricating such a structure. More specifically, the present disclosure describes a novel dielectric layer that is formed on the top surface of a III-V material where the dielectric layer comprises a first region in contact with the top surface of the III-V material crystalline and a second region adjacent to the first region and at the upper side of the dielectric layer. The dielectric layer has material properties different from traditional dielectric layers as it is composed of both crystalline and amorphous structures. The crystalline structure is at the interface with the III-V material (such as AlGaN or GaN) but gradually transitions into an amorphous structure, both within the same layer and both comprising the same material.

摘要翻译： 本公开提出了用于与III-V族材料体系一起使用的电介质材料的新型结构以及制造这种结构的方法。 更具体地，本公开描述了一种形成在III-V材料的顶表面上的新型电介质层，其中电介质层包括与III-V材料晶体的顶表面接触的第一区域和相邻的第二区域 到介电层的第一区域和上侧。 介电层具有与传统电介质层不同的材料特性，因为它由结晶和无定形结构组成。 晶体结构处于与III-V材料（例如AlGaN或GaN）的界面处，但是在同一层内并且两者都包含相同的材料而逐渐转变成非晶结构。