公开(公告)号：US20160003904A1

公开(公告)日：2016-01-07

申请号：US14827983

申请日：2015-08-17

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/31725 ,  G01R31/2856 ,  G01R31/2889 ,  G01R31/31727 ,  G01R31/3193

Abstract: Systems and methods of testing integrated circuits are disclosed. A system may include a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data. The system may also include a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency.

Abstract translation: 公开了测试集成电路的系统和方法。 系统可以包括数据压缩组件，以在第一时钟频率上压缩从被测集成电路接收的数据，以产生压缩数据。 系统还可以包括可操作地耦合到数据压缩部件的数据输出部件，以便以第二时钟频率将压缩数据传送到自动测试设备。

公开(公告)号：US09230609B2

公开(公告)日：2016-01-05

申请号：US13908973

申请日：2013-06-03

Applicant: Rambus Inc.

Inventor： Yohan Frans

IPC: G11C5/02 ,  G11C5/06 ,  H01L25/065

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/22 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Abstract translation: 封装的半导体器件包括数据引脚，第一存储器管芯和与第一存储器管芯堆叠的第二存储器管芯。 第一存储器管芯包括耦合到数据引脚的第一数据接口和具有多个存储体的第一存储器核心。 第二存储器管芯包括具有多个堤的第二存储器芯。 响应于第一命令信号和第二命令信号的并行列访问操作，第一存储器核心的相应组和第二存储器核心的相应组执行并行行存取操作。 第一管芯的第一数据接口将第一和第二管芯中的并行列访问操作的聚合数据提供给数据引脚。

公开(公告)号：US09229523B2

公开(公告)日：2016-01-05

申请号：US14694046

申请日：2015-04-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F9/38 ,  G06F12/08 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract translation: 存储器系统的存储器控​​制器组件将存储器访问请求存储在事务队列中，直到被服务，使得随着时间的推移，事务队列在被占用和空状态之间交替。 响应于检测到事务队列已经保持在空状态达预定时间，存储器控制器将存储器系统转换到低功率模式。 在向低功率模式的转变中，存储器控制器禁用在一个或多个附加存储器件的同步通信电路内对时间数据信号操作所需的一个或多个定时信号的振荡，并且还禁用同步通信中的一个或多个功耗电路 一个或多个存储器件的电路。

公开(公告)号：US20150378740A1

公开(公告)日：2015-12-31

申请号：US14852200

申请日：2015-09-11

Applicant: Rambus Inc.

Inventor： William C. MOYER ,  Jeffrey W. SCOTT

IPC: G06F9/38 ,  G06F11/10 ,  G06F9/30

CPC classification number: G06F9/3875 ,  G06F9/3004 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1076

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Abstract translation: 一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。 该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作 执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

公开(公告)号：US09225328B2

公开(公告)日：2015-12-29

申请号：US14696283

申请日：2015-04-24

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  H03K19/0175 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G06F13/40

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: In a non-volatile memory device having an array of non-volatile storage elements, command, address and data signals are received at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within the array of non-volatile storage elements. A control signal is received via a signaling path external to the non-volatile memory device, and an on-die termination element is switchably coupled to the time-multiplexed signaling line at least in part in response to a transition of the control signal from a first logic state to a second logic state.

Abstract translation: 在具有非易失性存储元件阵列的非易失性存储器件中，经由时间复用的外部信号线在各自的时间接收命令，地址和数据信号，该数据信号表示要存储在非阵列阵列内的数据 非易失存储元件。 经由非易失性存储器件外部的信令路径接收控制信号，并且片上终端元件至少部分地响应于来自控制信号的控制信号的转换而可切换地耦合到时间多路复用的信令线 第一逻辑状态到第二逻辑状态。

公开(公告)号：US20150370743A1

公开(公告)日：2015-12-24

申请号：US14691487

申请日：2015-04-20

Applicant: Rambus Inc.

Inventor： Michael J. Sobelman

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06F13/4286 ,  H01L2924/0002 ,  H04L25/0262 ,  H04L25/4908 ,  H01L2924/00

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract translation: 一种设备包括用于从第一通信链路接收信号的第一接口，其中所述接收信号包括带外（OOB）信息。 耦合到第一接口的检测器检测OOB信息。 耦合到检测器的编码器将OOB信息编码成一个或多个符号（例如，控制字符）。 第二接口耦合到编码器和第二通信链路（例如串行传输路径）。 第二接口在第二通信链路上发送符号。 该设备还包括用于防止终端设备的虚假存在检测的机制。

公开(公告)号：US09215103B2

公开(公告)日：2015-12-15

申请号：US14705761

申请日：2015-05-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L27/01 ,  H04L25/03 ,  H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

公开(公告)号：US20150355964A1

公开(公告)日：2015-12-10

申请号：US14830358

申请日：2015-08-19

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G11C11/401 ,  G11C29/52 ,  G11C2029/0411 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract translation: 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

公开(公告)号：US20150348612A1

公开(公告)日：2015-12-03

申请号：US14799362

申请日：2015-07-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract translation: 集成电路包括具有控制定时域和数据定时域的物理层接口，以及响应于第一事件而在功率节省模式改变期间实现控制定时域的电路，并且响应于数据定时域 到第二个事件。 控制定时域可以包括耦合到命令和地址路径的接口电路，并且数据定时域可以包括耦合到数据路径的接口电路。

公开(公告)号：US20150341128A1

公开(公告)日：2015-11-26

申请号：US14817607

申请日：2015-08-04

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04B17/29 ,  H04L27/01 ,  H04L25/03

CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用在采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。