公开(公告)号：US20060180346A1

公开(公告)日：2006-08-17

申请号：US11357503

申请日：2006-02-16

Applicant: Suzanne Knight ,  Douglas Thomas

Inventor： Suzanne Knight ,  Douglas Thomas

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K3/4623 ,  H05K1/112 ,  H05K3/0047 ,  H05K3/306 ,  H05K3/308 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/1059 ,  H05K2203/061 ,  H05K2203/1476 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The drilling and plating of high aspect ratio blind via holes in a multilayer printed circuit board are disclosed. A via hole is drilled through a sub-composite structure. The walls of the via hole are plated with a conductive material, and the hole is filled with a conductive medium. The sub-composite structure proceeds through the remainder of the processing that is necessary to manufacture the printed circuit board up to the completion of the solder mask step. The conductive medium of the via hole is drilled out to achieve a hole size that is of the desired diameter as required by the printed circuit board design.

Abstract translation: 公开了多层印刷电路板中高纵横比盲孔的钻孔和电镀。 通过子复合结构钻通孔。 通孔的壁镀有导电材料，并且该孔填充有导电介质。 子复合结构进行到制造印刷电路板直到完成焊接掩模步骤所需的处理的其余部分。 钻出通孔的导电介质以实现根据印刷电路板设计所要求的所需直径的孔尺寸。

公开(公告)号：US07087845B2

公开(公告)日：2006-08-08

申请号：US10508538

申请日：2004-01-28

Applicant: Hiroshi Tohkairin ,  Kenji Sakakibara ,  Hideki Kabune

Inventor： Hiroshi Tohkairin ,  Kenji Sakakibara ,  Hideki Kabune

IPC: H05K1/00

CPC classification number: H05K1/0207 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/10689 ,  H01L2924/00

Abstract: The present invention is characterized in that in a metal-core multilayer printed wiring board (1) which is obtained by forming one or more of at least inner layers of a laminate having a insulating layer and a conductor layer stacked alternately from a metal plate and has the metal plate as a core, the metal plate (13) is disposed below a site on which a heating element (10) is to be mounted, a surface layer over which the heating element (10) is to be mounted is connected to the metal plate (13) of the inner layer via a BVH (12) and a heat radiation layer (14) is formed over the surface layer. The present invention makes it possible to efficiently radiate heat, which has been released from the heating element, to the outside of the printed wiring board without impairing the packaging density of circuits and at the same time, to mount another element on the side opposite to the side on which the heating element exists.

Abstract translation: 本发明的特征在于，在金属芯多层印刷电路板（1）中，所述金属芯多层印刷电路板（1）通过形成由金属板交替堆叠的具有绝缘层和导体层的层叠体的至少内层中的一个或多个而获得， 将金属板作为芯，将金属板（13）设置在要安装加热元件（10）的位置的下方，将要安装加热元件（10）的表面层连接到 通过BVH（12）和散热层（14）在内层的金属板（13）上形成。 本发明使得可以有效地将已经从加热元件释放的热量辐射到印刷电路板的外部，而不会损害电路的封装密度，同时在另一个元件的相反侧安装另一个元件 加热元件所在的一侧。

公开(公告)号：US20060163740A1

公开(公告)日：2006-07-27

申请号：US11391375

申请日：2006-03-29

Applicant: Masaki Ohno ,  Masanori Tamaki

Inventor： Masaki Ohno ,  Masanori Tamaki

IPC: H05K1/09

CPC classification number: H05K1/114 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A semiconductor mounting board 80 is prepared by electrically joining an IC chip 70 via an interposer 60 of high rigidity to external pads 41 and internal pads 43, which are formed on the uppermost surface of a build-up layer 30. When the IC chip 70 generates heat, since pads 41 are positioned away from the center, a large shearing stress is applied to the portions at which pads 41 are joined to the interposer 60 in comparison to the portions at which pads 43 are joined to the interposer 60. Here, pads 41 are formed at substantially flat wiring portions and thus when joined to the interposer 60 by means of solder bumps 51, voids and angled portions, at which stress tends to concentrate, are not formed in the interiors of solder bumps 51. The joining reliability is thus high.

Abstract translation: 通过将IC芯片70通过高刚性的插入件60电连接到形成在积聚层30的最上表面上的外部焊盘41和内部焊盘43来制备半导体安装板80.当IC芯片70 产生热量，因为焊盘41位于远离中心的位置，与衬垫43接合到插入器60的部分相比，大的剪切应力施加到焊盘41接合到插入件60的部分。这里， 焊盘41形成在基本上平坦的布线部分处，因此当通过焊料凸块51接合到插入件60时，不会在焊料凸块51的内部形成空隙和倾斜部分，其中应力趋于集中。连接可靠性 因此高。

公开(公告)号：US07064427B2

公开(公告)日：2006-06-20

申请号：US10863700

申请日：2004-06-07

Applicant: Stephen Chung ,  Jungle Lee ,  Shinn-Juh Lay ,  Randy Wu ,  Huey-Ru Chang ,  Yu-Mei Cheng

Inventor： Stephen Chung ,  Jungle Lee ,  Shinn-Juh Lay ,  Randy Wu ,  Huey-Ru Chang ,  Yu-Mei Cheng

IPC: H01L23/04

CPC classification number: H05K1/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10674

Abstract: A unitary buried array capacitor and microelectronic structures incorporating such capacitors are disclosed. A unitary buried array capacitor can be formed by a top layer of electrode, a middle layer of dielectric, and a bottom layer of electrode. A first electrode lead, a second electrode lead and at least one interconnect line pass through the three layers while only the first electrode lead making electrical contact with the top layer of electrode and only the second electrode lead making electrical contact with the bottom electrode.

Abstract translation: 公开了一种整体埋地阵列电容器和结合这种电容器的微电子结构。 单一埋地阵列电容器可以由电极的顶层，电介质的中间层和电极的底层形成。 第一电极引线，第二电极引线和至少一个互连线穿过三层，而只有第一电极引线与电极的顶层电接触，并且仅第二电极引线与底部电极电接触。

公开(公告)号：US07060595B2

公开(公告)日：2006-06-13

申请号：US10627609

申请日：2003-07-28

Applicant: In-De Ou ,  Chih-Pin Hung ,  Chia-Shang Chen ,  Kuang-Hua Lin ,  Shin-Hua Chao

Inventor： In-De Ou ,  Chih-Pin Hung ,  Chia-Shang Chen ,  Kuang-Hua Lin ,  Shin-Hua Chao

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/043 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H01L2924/00

Abstract: A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.

Abstract translation: 电路基板包括板，多个金属层和绝缘体。 该板具有多个导电迹线层和形成在其中的通孔。 金属层形成在通孔的内壁上，并且每个金属层电连接到其对应的导电迹线层。 通孔填充有绝缘体，使得每个金属层彼此电隔离。 此外，本发明还提供了电路基板的制造方法。

公开(公告)号：US20060115770A1

公开(公告)日：2006-06-01

申请号：US11058998

申请日：2005-02-15

Applicant: Jong Hong ,  Chang Ryu ,  Ho Jeon ,  Seok Lee

Inventor： Jong Hong ,  Chang Ryu ,  Ho Jeon ,  Seok Lee

IPC: G03C5/00

CPC classification number: H05K1/162 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/108 ,  H05K3/181 ,  H05K3/184 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/0551

Abstract: Disclosed is a PCB including an embedded capacitor, in which a dielectric layer and an upper electrode layer are formed after a lower electrode layer of the embedded capacitor is formed, thereby providing a microcircuit pattern on a circuit layer having a lower electrode layer formed thereon, and a method of fabricating the same.

Abstract translation: 公开了一种在嵌入式电容器的下电极层形成之后形成介质层和上电极层的嵌入式电容器的PCB，从而在其上形成有下电极层的电路层上提供微电路图案， 及其制造方法。

公开(公告)号：US07049929B1

公开(公告)日：2006-05-23

申请号：US10136964

申请日：2002-05-01

Applicant: Joseph Fjelstad

Inventor： Joseph Fjelstad

IPC: H01C1/012

CPC classification number: H01C17/065 ,  H01C7/005 ,  H05K1/115 ,  H05K1/167 ,  H05K3/4076 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2203/0733

Abstract: Circuit panels are provided with resistors in vias extending between the top and bottom surfaces of the panels. The resistors may be formed by depositing a composite in each via, as by depositing a dispersion of a conductive material and a dielectric or by depositing one or more thin layers of a conductor. The resistors may be disposed at interior locations buried within a multilayer circuit board formed by laminating one or more panels having such resistors with one or more additional elements.

Abstract translation: 电路板在电路板的顶表面和底表面之间设有通孔中的电阻。 电阻器可以通过在每个通孔中沉积复合材料形成，如通过沉积导电材料和电介质的分散体或通过沉积导体的一个或多个薄层而形成的。 电阻器可以被布置在埋在多层电路板内的内部位置，所述多层电路板通过层压具有这种电阻器的一个或多个面板与一个或多个附加元件而形成。

公开(公告)号：US20060091188A1

公开(公告)日：2006-05-04

申请号：US10976980

申请日：2004-10-29

Applicant: Cheng Tay ,  Pek Tan ,  Swee Cheng ,  Eng Yap

Inventor： Cheng Tay ,  Pek Tan ,  Swee Cheng ,  Eng Yap

IPC: B23K31/02

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L21/486 ,  H05K3/3484 ,  H05K2201/0266 ,  H05K2201/035 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/043 ,  H05K2203/1476

Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括用形成第一尺寸的焊球的焊膏填充在焊盘中形成的微孔; 以及用包括第二尺寸的焊球的焊膏涂覆所述接合焊盘，其中所述第二尺寸大于所述第一尺寸。

公开(公告)号：US07035082B2

公开(公告)日：2006-04-25

申请号：US10895113

申请日：2004-07-21

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu

IPC: H01G4/228

CPC classification number: H01G4/012 ,  H01G4/228 ,  H05K1/162 ,  H05K2201/09509 ,  H05K2201/09672

Abstract: A structure and method for manufacturing multi-electrode capacitor within a PCB is used to form a multi-electrode capacitor with a plurality of metal laminates coupled each other and employing the characteristics of the edge-coupled effect therein. the present invention can provide efficient capacitance from the capacitor with the smallest area. The present invention is applied to promote the capability of noise-restraint of the capacitive substrate in a high-frequency/speed system, and further achieves the purpose of regular circuit design with the smallest area in the future development.

Abstract translation: 使用用于在PCB内制造多电极电容器的结构和方法来形成具有彼此耦合的多个金属层压体的多电极电容器，并且采用其中的边缘耦合效应的特性。 本发明可以从具有最小面积的电容器提供有效的电容。 本发明应用于提​​高高频/速度系统中电容基板的噪声抑制能力，进一步达到了将来开发面积最小的规则电路设计的目的。

公开(公告)号：US20060042824A1

公开(公告)日：2006-03-02

申请号：US11260077

申请日：2005-10-27

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H05K5/06

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.