公开(公告)号：US09048197B2

公开(公告)日：2015-06-02

申请号：US12709425

申请日：2010-02-19

Applicant: Byung Tai Do ,  Heap Hoe Kuan

Inventor： Byung Tai Do ,  Heap Hoe Kuan

IPC: H01L23/22 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/27 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.

Abstract translation: 一种集成电路封装系统，包括：为基板提供保护涂层; 在单独的工艺中将标记膜附着到支撑构件上; 连接保护涂层和标签膜; 并对衬底，保护涂层和标记膜进行切割，形成集成电路封装系统。

公开(公告)号：US20150140736A1

公开(公告)日：2015-05-21

申请号：US14548064

申请日：2014-11-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85

Abstract: A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire.

Abstract translation: 半导体器件具有沉积在第一半导体管芯上的第一半导体管芯和第一密封剂。 在第一半导体管芯和第一密封剂上形成互连结构。 包括导电通孔的模块化互连结构设置成与第一半导体管芯相邻。 第一密封剂沉积在模块化互连结构上。 在延伸到模块化互连结构或互连结构的第一密封剂中形成开口。 第二半导体管芯设置在第一半导体管芯上。 接合线形成在第二半导体管芯上并延伸到第一密封剂中的开口中。 帽形成在第二半导体管芯的有源区上。 第二密封剂沉积在第二半导体管芯和接合线上。 或者，在第二半导体管芯和接合线上形成盖。

公开(公告)号：US08994192B2

公开(公告)日：2015-03-31

申请号：US13327651

申请日：2011-12-15

Applicant: DaeSik Choi

Inventor： DaeSik Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L23/562 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511

Abstract: A method of manufacture of an integrated circuit packaging system comprising: providing a package carrier; mounting an integrated circuit to the package carrier; and forming a perimeter antiwarpage structure on and along a perimeter of the package carrier.

Abstract translation: 一种制造集成电路封装系统的方法，包括：提供封装载体; 将集成电路安装到封装载体上; 以及在包装载体的周边上并沿其周边形成周边的防瓦结构。

公开(公告)号：US08994184B2

公开(公告)日：2015-03-31

申请号：US13887180

申请日：2013-05-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/544 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95121 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4647 ,  H05K2201/09518 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

Abstract translation: 半导体器件具有在衬底上形成多个导电通孔和导电层的衬底。 半导体管芯安装在载体上。 衬底被安装到与载体相对的半导体管芯上。 在半导体管芯周围的衬底和载体之间沉积密封剂。 通过衬底和密封剂形成多个导电TMV。 导电TMV从密封剂突出以帮助互连结构的对准。 导电TMV电连接到导电层和导电通孔。 移除载体并且在与衬底相对的密封剂和半导体管芯的表面上形成互连结构。 互连结构电连接到导电TMV。 多个半导体器件可以通过衬底层叠并电连接，导电TMV和互连结构。

公开(公告)号：US08975111B2

公开(公告)日：2015-03-10

申请号：US13170116

申请日：2011-06-27

Applicant: Yaojian Lin ,  Haijing Cao

Inventor： Yaojian Lin ,  Haijing Cao

IPC: H01L21/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/18 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2221/68368 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.

Abstract translation: 制造半导体器件的方法包括提供用于支撑半导体器件的晶片。 绝缘层设置在晶片的顶表面上。 该方法包括在超过200℃的温度下在晶片的顶表面上形成第一互连结构，在与第一互连结构电接触的晶片上形成金属柱，将半导体部件连接到第一互连结构 ，并在半导体部件上形成密封剂。 蚀刻密封剂以暴露金属柱的一部分。 任选地在密封剂上形成缓冲层。 该方法包括在温度低于200℃的金属柱上与密封剂形成第二互连结构，并且移除与晶片顶表面相对的晶片背面的一部分。

公开(公告)号：US08957515B2

公开(公告)日：2015-02-17

申请号：US11936516

申请日：2007-11-07

Applicant: Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Abelardo Jr. Hadap Advincula ,  Lionel Chien Hui Tay

Inventor： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Abelardo Jr. Hadap Advincula ,  Lionel Chien Hui Tay

IPC: H01L23/48 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49548 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed.

Abstract translation: 集成电路封装系统包括：形成具有外部互连之间的相交区域的外部互连阵列; 去除用于在外部互连之间形成隔离孔的交叉区域; 在外部互连上安装集成电路管芯; 连接集成电路管芯和外部互连件之间的内部互连; 以及在所述集成电路管芯上形成封装封装，所述外部互连部分露出。

公开(公告)号：US08952529B2

公开(公告)日：2015-02-10

申请号：US13303019

申请日：2011-11-22

Applicant: JaeHyun Lee ,  SunJae Kim ,  JoongGi Kim

Inventor： JaeHyun Lee ,  SunJae Kim ,  JoongGi Kim

IPC: H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/528 ,  H01L21/4867 ,  H01L21/563 ,  H01L21/565 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5221 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的多个凸点的半导体管芯。 具有第一和第二段的第一导电层形成在衬底的表面上，其中第一通气口分隔第一段和第二段的端部，第二通气口分隔第二段和第一段的一端。 第二导电层形成在衬底的表面上以电连接第一段和第二段。 第二导电层的厚度可以小于第一导电层的厚度，以形成第一通气孔和第二通气口。 将半导体管芯安装到衬底上，其中凸块与第一段和第二段对准。 凸块的回流材料的凸起材料被引导到第一通风口和第二排气口中。

公开(公告)号：US08951839B2

公开(公告)日：2015-02-10

申请号：US12724354

申请日：2010-03-15

Applicant: Yaojian Lin ,  Pandi Chelvam Marimuthu

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L21/76829 ,  H01L21/4832 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Abstract translation: 半导体器件具有安装在载体上的半导体管芯。 封装剂沉积在载体和半导体管芯上。 载体被移除。 在密封剂和模具的第一表面上形成第一互连结构。 在密封剂和模具的第二表面上形成第二互连结构。 在第一互连结构之上形成第一保护层，并且在形成通孔之前在第二互连结构上形成第二保护层。 通过第二互连结构，密封剂和第一互连结构形成多个通孔。 在通孔中形成第一导电层以电连接第一互连结构和第二互连结构。 绝缘层形成在第一互连结构和第二互连结构之上，并且形成在通孔中。 分立半导体部件可以安装到第一互连结构。

公开(公告)号：US20150028496A1

公开(公告)日：2015-01-29

申请号：US14514190

申请日：2014-10-14

Applicant: STATS CHIPPAC, LTD.

Inventor： Henry D. Bathan ,  Zigmund R. Camacho ,  Jairus L. Pisigan

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract translation: 通过在第一半导体管芯上形成第一和第二互连结构来制造半导体器件。 在第一管芯附近形成第三互连结构。 第二半导体管芯安装在第二和第三互连结构上。 密封剂沉积在第一和第二管芯以及第一，第二和第三互连结构上。 第二管芯的背面基本上与第一互连结构共面，并且第一半导体管芯的背面基本上与第三互连结构共面。 第一互连结构具有与第二互连结构的高度和第二管芯的厚度的组合基本相同的高度。 第三互连结构具有与第二互连结构的高度和第一管芯的厚度的组合基本相同的高度。

公开(公告)号：US08937372B2

公开(公告)日：2015-01-20

申请号：US11689317

申请日：2007-03-21

Applicant: Jae Hak Yee ,  Junwoo Myung

Inventor： Jae Hak Yee ,  Junwoo Myung

IPC: H01L21/02 ,  H01L23/28 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L23/3107 ,  H01L24/97 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00

Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.

Abstract translation: 一种集成电路封装系统包括一个在线条带，将一个集成电路管芯连接在一条直线条上，以及一个模塑材料，该模制材料具有一个模制部分，该模制部分具有一个模制条形突出部，该模制部分由此形成。