专利检索 ap:("Chen-Hua Yu" OR "Shau-Lin Shue" OR "Hsiang-Huan Lee" OR "Ching-Fu Yeh") AND inv:"Chen-Hua Yu" 第 7 页

61.

发明授权
Stress-alleviation layer for LED structures 有权
标题翻译： LED结构应力消除层

公开(公告)号：US08779445B2

公开(公告)日：2014-07-15

申请号：US12179160

申请日：2008-07-24

申请人： Chen-Hua Yu , Hung-Ta Lin , Ding-Yuan Chen , Wen-Chih Chiou , Chia-Lin Yu

发明人： Chen-Hua Yu , Hung-Ta Lin , Ding-Yuan Chen , Wen-Chih Chiou , Chia-Lin Yu

IPC分类号： H01L29/18

CPC分类号： H01L33/44 , H01L33/005 , H01L33/007 , H01L33/0079 , H01L33/08 , H01L33/12

摘要： A light emitting diodes (LEDs) is presented. The LED includes a stress-alleviation layer on a substrate. Open regions and stress-alleviation layer regions are formed on the substrate. Epitaxial layers are disposed on the substrate, at least in the open regions therein, thereby forming an LED structure. The substrate is diced through at least a first portion of the stress-alleviation regions, thereby forming the plurality of LEDs.

摘要翻译： 提供了发光二极管（LED）。 LED在衬底上包括应力消除层。在基板上形成开放区域和应力缓和层区域。外延层至少在其中的开放区域中设置在基板上，从而形成LED结构。通过应力缓解区域的至少第一部分切割衬底，从而形成多个LED。

62.

发明授权
Packages with passive devices and methods of forming the same 有权
标题翻译：带无源器件的封装及其形成方法

公开(公告)号：US08680647B2

公开(公告)日：2014-03-25

申请号：US13464081

申请日：2012-05-04

申请人： Chen-Hua Yu , Shang-Yun Hou , Der-Chyang Yeh , Shuo-Mao Chen , Chiung-Han Yeh , Yi-Jou Lin

发明人： Chen-Hua Yu , Shang-Yun Hou , Der-Chyang Yeh , Shuo-Mao Chen , Chiung-Han Yeh , Yi-Jou Lin

IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L23/64

CPC分类号： H01L21/56 , H01L23/3192 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L23/64 , H01L24/19 , H01L27/016 , H01L28/00 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/18162 , H01L2924/19011 , H01L2924/1903 , H01L2924/19031 , H01L2924/19033 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00012 , H01L2924/00

摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

摘要翻译： 一种器件包括衬底，衬底上的金属焊盘以及具有在金属焊盘上的部分的钝化层。后钝化互连（PPI）线设置在钝化层上并电耦合到金属焊盘。爆炸性冶金（UBM）被布置在电气耦合到PPI线路上。无源设备包括与UBM处于相同水平的部分。无源器件的部分由与UBM相同的材料形成。

63.

发明授权
Connector design for packaging integrated circuits 有权

公开(公告)号：US08664760B2

公开(公告)日：2014-03-04

申请号：US13343582

申请日：2012-01-04

申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

IPC分类号： H01L23/48 , H01L23/52 , H01L29/40

CPC分类号： H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

摘要： A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

64.

发明授权
Method for designing a package and substrate layout 有权
标题翻译：设计封装和基板布局的方法

公开(公告)号：US08664041B2

公开(公告)日：2014-03-04

申请号：US13445699

申请日：2012-04-12

申请人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo

发明人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo

IPC分类号： H01L21/44 , H01L21/48 , H01L21/50

CPC分类号： G06F17/5068 , H01L23/3192 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11849 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01074 , H01L2224/1144

摘要： A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.

摘要翻译： 一种用于防止在跟踪轨迹结构中的相邻金属迹线桥接的方法和装置。一个实施例包括确定包装部件的热膨胀系数（CTE）和工艺参数。然后分析设计参数，并且可以基于包装部件的CTE和工艺参数来修改设计参数。

65.

发明授权
Photoactive compound gradient photoresist 有权
标题翻译：光敏化合物梯度光刻胶

公开(公告)号：US08647796B2

公开(公告)日：2014-02-11

申请号：US13192113

申请日：2011-07-27

申请人： Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo

发明人： Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo

IPC分类号： G03F7/00

CPC分类号： H01L23/5226 , G03F7/0045 , G03F7/095 , H01L21/311 , H01L21/76804 , H01L24/24 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/24146 , H01L2224/73259 , H01L2224/8203 , H01L2224/82101 , H01L2224/82106 , H01L2224/94 , H01L2225/06524 , H01L2924/10253 , H01L2924/1431 , H01L2924/1434 , H01L2224/82 , H01L2224/81

摘要： A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.

摘要翻译： 提供了一种用于在半导体衬底上形成光致抗蚀剂的系统和方法。一个实施方案包括具有浓度梯度的光致抗蚀剂。浓度梯度可以通过使用一系列干膜光致抗蚀剂形成，其中每个单独的干膜光致抗蚀剂具有不同的浓度。单独的干膜光致抗蚀剂可以单独形成，然后在图案化之前放置在半导体衬底上。一旦被图案化，通过光致抗蚀剂的开口可以具有锥形侧壁，允许更好地覆盖种子层，以及更均匀的工艺以通过光致抗蚀剂形成导电材料。

66.

发明申请
CIS Chips and Methods for Forming the Same 有权
标题翻译： CIS芯片及其形成方法

公开(公告)号：US20140027872A1

公开(公告)日：2014-01-30

申请号：US13558063

申请日：2012-07-25

申请人： Chen-Hua Yu , Wen-Chih Chiou , Jing-Cheng Lin

发明人： Chen-Hua Yu , Wen-Chih Chiou , Jing-Cheng Lin

IPC分类号： H01L31/0232 , H01L31/18

CPC分类号： H01L27/14689 , H01L21/6835 , H01L21/76834 , H01L21/76879 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L31/02002 , H01L31/02327 , H01L2221/68327 , H01L2221/6834 , H01L2224/023 , H01L2224/13101 , H01L2924/014 , H01L2924/00014

摘要： A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.

摘要翻译： 一种器件包括半导体衬底，在半导体衬底的前表面处的图像传感器和图像传感器上的多个电介质层。滤色器和微透镜设置在多个介电层上并与图像传感器对准。穿通通孔穿过半导体衬底。再分配线（RDL）设置在多个介电层上，其中RDL电连接到通孔。聚合物层覆盖RDL。

67.

发明申请
Interconnect Structure for CIS Flip-Chip Bonding and Methods for Forming the Same 有权
标题翻译： CIS倒装芯片接合的互连结构及其形成方法

公开(公告)号：US20140015086A1

公开(公告)日：2014-01-16

申请号：US13546847

申请日：2012-07-11

申请人： Chen-Hua Yu , Yung Ching Chen , Chien-Hsun Lee , Mirng-Ji Lii

发明人： Chen-Hua Yu , Yung Ching Chen , Chien-Hsun Lee , Mirng-Ji Lii

IPC分类号： H01L31/02

CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/14683 , H01L31/02002 , H01L2924/0002 , H01L2924/01322 , H01L2924/12042 , H01L2924/15787 , H01L2924/00 , H01L2924/00012

摘要： A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.

摘要翻译： 一种设备包括在图像传感器芯片的表面处的金属焊盘，其中图像传感器芯片包括图像传感器。螺柱凸块设置在金属垫的上方并电连接到金属垫。凸起凸块包括凸起区域和连接到凸起区域的尾部区域。尾部区域包括基本上垂直于金属垫的顶表面的金属线部分。尾部区域足够短，能够抵抗重力。

68.

发明授权
Liner formation in 3DIC structures 有权
标题翻译： 3DIC结构中的衬垫形成

公开(公告)号：US08629066B2

公开(公告)日：2014-01-14

申请号：US13562101

申请日：2012-07-30

申请人： Ching-Yu Lo , Hung-Jung Tu , Hai-Ching Chen , Tien-I Bao , Wen-Chih Chiou , Chen-Hua Yu

发明人： Ching-Yu Lo , Hung-Jung Tu , Hai-Ching Chen , Tien-I Bao , Wen-Chih Chiou , Chen-Hua Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L2221/68372 , H01L2224/0557 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/05552 , H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

摘要翻译： 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。