利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1213 条记录 (耗时 0.065 秒)

    Fabrication method of packaging substrate
    75.
    发明授权
    Fabrication method of packaging substrate 有权
    包装基材的制造方法

    公开(公告)号：US09455159B2

    公开(公告)日：2016-09-27

    申请号：US14866106

    申请日：2015-09-25

    申请人： Siliconware Precision Industries Co., Ltd.

    发明人： Wei-Ping Wang ,  Pang-Chun Lin ,  Chin-Chih Hsiao ,  Kuan-I Cheng ,  Cheng-Wen Chiu

    IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

    CPC分类号： H01L21/4857 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.

    摘要翻译： 一种用于制造封装衬底的方法，包括：提供具有形成在第一金属层上的第一金属层和第二金属层的载体; 在所述第二金属层上形成第一电路层，并在所述第二金属层的边缘上形成分离部分，使得所述分离部分与所述第一电路层隔开; 在所述第二金属层和所述第一电路层上形成介电层，使得所述第一电路层和所述分离部分嵌入在所述电介质层中，并且所述电介质层的部分形成在所述第一电路层与所述分离部之间; 在所述电介质层上形成第二电路层; 并且在分离部分上施加力以便去除第一金属层和载体，从而保持第一电路层的完整性。

    Package structure and fabrication method thereof
    76.
    发明授权
    Package structure and fabrication method thereof 有权
    封装结构及其制造方法

    公开(公告)号：US09425119B2

    公开(公告)日：2016-08-23

    申请号：US14273952

    申请日：2014-05-09

    申请人： Siliconware Precision Industries Co., Ltd.

    发明人： Hong-Da Chang ,  Shih-Kuang Chiu

    IPC分类号： H01L23/28 ,  H01L21/768 ,  B81B7/00 ,  G01L19/00 ,  G01L19/14 ,  H01L23/10

    CPC分类号： H01L23/28 ,  B81B7/0061 ,  B81B7/007 ,  B81B2207/098 ,  G01L19/0076 ,  G01L19/147 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2924/00014

    摘要： A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.

    摘要翻译： 提供了一种封装结构，其包括：具有带有凹槽的表面的晶片，封闭凹槽的开口端的薄膜和电触头; 芯片，其表面具有导电层，与凹部相对的表面和位于凹部周边的密封环，芯片设置在晶片上，密封环围绕薄膜，电触点位于 密封环外; 形成在晶片上用于封装芯片和电触点的密封剂; 多个次级导电线嵌入密封剂中，其一端从密封剂的顶表面露出，另一端与电触点电连接; 以及穿透晶片并与凹部连通的通孔，从而降低了封装结构的制造成本和尺寸。

    Semiconductor package and fabrication method thereof
    80.
    发明授权
    Semiconductor package and fabrication method thereof 有权
    半导体封装及其制造方法

    公开(公告)号：US09082723B2

    公开(公告)日：2015-07-14

    申请号：US14143700

    申请日：2013-12-30

    申请人： Siliconware Precision Industries Co., Ltd

    发明人： Tzu-Chieh Chen ,  Shih-Chao Chiu ,  Chia-Cheng Chen

    IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L24/32 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/00

    摘要： A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.

    摘要翻译： 提供一种半导体封装，其包括：具有相对的第一和第二表面的第一介电层和穿透第一表面和第二表面的空腔; 第一电路层，其被嵌入在所述第一电介质层中并从所述第一介电层的所述第一表面露出; 至少形成在所述空腔中并且与所述第一介电层的所述第一表面相邻的粘合构件; 设置在所述粘合构件上的电子元件; 第二电介质层，形成在所述第一介电层的所述第二表面上并且在所述空腔中，以封装所述粘合剂构件和所述电子元件; 形成在所述第二电介质层上的第二电路层; 以及形成在第二电介质层中的多个导电通孔，用于电连接第二电路层和电子元件，由此减小封装尺寸和成本并增加布线空间和柔性。