公开(公告)号：US20050051824A1

公开(公告)日：2005-03-10

申请号：US10967436

申请日：2004-10-18

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/04 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US06703705B2

公开(公告)日：2004-03-09

申请号：US09996054

申请日：2001-11-28

申请人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

发明人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

IPC分类号： H01L2352

CPC分类号： H01L24/81 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

摘要翻译： 半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

公开(公告)号：US5943547A

公开(公告)日：1999-08-24

申请号：US926369

申请日：1997-09-09

申请人： Shintaro Yamamichi ,  Pierre Yves Lesaicherre

发明人： Shintaro Yamamichi ,  Pierre Yves Lesaicherre

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/55

摘要： In a capacitor including a silicon substrate and an insulating layer formed on the silicon substrate having a contact hole, a lower electrode layer including a silicon diffusion preventing conductive layer and an oxidation resistance conductive layer, an upper electrode layer, and a high dielectric constant layer therebetween, the silicon diffusion preventing layer is located on or within the contact hole and is isolated from the high dielectric constant layer. The high dielectric constant layer is formed on an upper surface and a side surface of the oxidation resistance conductive layer.

摘要翻译： 在包括硅衬底和形成在具有接触孔的硅衬底上的绝缘层的电容器中，包括防硅扩散导电层和抗氧化电阻导电层的下电极层，上电极层和高介电常数层 其间，硅扩散防止层位于接触孔的上方或内部，并与高介电常数层隔离。 高介电常数层形成在抗氧化导电层的上表面和侧表面上。

公开(公告)号：US20100044845A1

公开(公告)日：2010-02-25

申请号：US12298737

申请日：2007-04-27

申请人： Takuo Funaya ,  Shintaro Yamamichi

发明人： Takuo Funaya ,  Shintaro Yamamichi

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10969 ,  H05K2203/061 ,  H01L2924/00

摘要： [Problem to be Solved] There are provided a circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate which enable to directly implement the surface mounting and so on of electronic components on the conductive wiring without forming solder resist, and also which enable to enhance high speed transmission characteristics and to enlarge wiring rule for the electrode terminal of the function element to be contained therein, and to implement with excellent workability and reliability when connecting the electronic device.[Solution] A circuit substrate comprising a function element 1 with an electrode terminal 5 a base member containing the function element 1 therein and having at least one layer of a conductive wiring formed on its front side face and rear side face respectively, and a via 6 connecting the electrode terminal 5 with the conductive wiring 3 formed on the base member, wherein the conductive wiring formed on either one of the front side face and the rear side face of the base member is arranged such that a surface exposed outside from the base member is in the same plane with or inside a surface of the base member on which the conductive wiring is formed.

摘要翻译： [待解决的问题]提供了一种用于电路基板的电路基板，电子器件布置和制造工艺，其能够直接实现导电布线上的电子部件的表面安装等而不形成阻焊剂，并且还 能够提高高速传输特性，并且扩大要包含在其中的功能元件的电极端子的布线规则，并且在连接电子设备时实现优异的可加工性和可靠性。 [解决方案]一种电路基板，包括具有电极端子5的功能元件1，分别在其前侧面和后侧面上形成有至少一层导电布线的基座部件，其中包括功能元件1，以及通孔 6，其将电极端子5与形成在基底构件上的导电布线3连接，其中形成在基底构件的前侧面和后侧面中的任一个上的导电布线布置成使得从底部暴露出的表面 构件与形成有导电布线的基底构件的表面位于同一平面内。

公开(公告)号：US20080064147A1

公开(公告)日：2008-03-13

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro IIZUKA ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro IIZUKA ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/82 ,  H01L21/8242

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2 2，（Zr x x，Hf）2， （0

公开(公告)号：US20070152256A1

公开(公告)日：2007-07-05

申请号：US11637147

申请日：2006-12-12

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L29/94

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0

摘要翻译： 一种具有形成在同一半导体芯片上的逻辑部分和存储部分的半导体器件，包括：形成在逻辑部分中并具有栅电极和源极和漏极区域的第一晶体管，以及形成在存储部分中的第二晶体管， 栅极电极，源极和漏极区域以及电容器，电容器是MIM结构，并且具有夹在其间的上部和下部金属电极和电容器电介质膜，所述电容器电介质膜由介电材料形成，所述绝缘材料选自 由ZrO2，Hf92，（Zrx，Hf1-x）O2（0

公开(公告)号：US06949815B2

公开(公告)日：2005-09-27

申请号：US10746603

申请日：2003-12-23

申请人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

发明人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

IPC分类号： H05K3/34 ,  H01L21/60 ,  H01L21/822 ,  H01L23/12 ,  H01L23/50 ,  H01L23/64 ,  H01L27/04 ,  H01L23/52 ,  H01L23/32 ,  H01L23/48 ,  H01G9/05

CPC分类号： H01L24/81 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

摘要翻译： 半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

公开(公告)号：US5539613A

公开(公告)日：1996-07-23

申请号：US73066

申请日：1993-06-08

申请人： Shintaro Yamamichi ,  Toshiyuki Sakuma ,  Yoichi Miyasaka

发明人： Shintaro Yamamichi ,  Toshiyuki Sakuma ,  Yoichi Miyasaka

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92

CPC分类号： H01L28/40

摘要： In a semiconductor device which has a substrate, at least one thin film capacitor having a lower electrode layer deposited on the substrate, a dielectric layer overlaid on the lower electrode layer, and an upper electrode layer stacked on the dielectric layer, the lower electrode layer is surrounded by an insulator layer of Si.sub.3 N.sub.4.

摘要翻译： 在具有衬底的半导体器件中，至少一个薄膜电容器具有沉积在衬底上的下电极层，覆盖在下电极层上的电介质层和堆叠在电介质层上的上电极层，下电极层 被Si3N4的绝缘体层包围。

公开(公告)号：US20120021357A1

公开(公告)日：2012-01-26

申请号：US13146841

申请日：2010-01-29

申请人： Katsumi Maeda ,  Shintaro Yamamichi

发明人： Katsumi Maeda ,  Shintaro Yamamichi

IPC分类号： G03F7/20 ,  G03F7/028

CPC分类号： G03F7/0392 ,  C08F220/30 ,  C08F220/58 ,  G03F7/0045

摘要： A photosensitive insulating resin composition, comprising a polymer, a photosensitizer, and an amide derivative that is expressed by the following general formula (1); (in formula (1), R1 represents a bivalent alkyl group, R2 represents a hydrocarbon group with a carbon number of 1 to 10, and R3 represents a hydrogen atom or an alkyl group with a carbon number of 1 to 4.)

摘要翻译： 一种感光绝缘树脂组合物，其包含由以下通式（1）表示的聚合物，光敏剂和酰胺衍生物; （式（1）中，R 1表示二价烷基，R 2表示碳数为1〜10的烃基，R 3表示氢原子或碳原子数为1〜4的烷基）

公开(公告)号：US07745736B2

公开(公告)日：2010-06-29

申请号：US11341445

申请日：2006-01-30

申请人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

发明人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K3/205 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H05K1/113 ,  H05K3/107 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/0384 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate includes a first interconnection pattern formed of the first interconnection which includes at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.

摘要翻译： 互连基板设置有在底面具有下沉部分的基底绝缘膜，设置在凹陷部分中的第一互连，形成在基底绝缘膜中的通孔，以及连接到第一互连件的第二互连 通过所述通孔内的导体，并形成在所述基底绝缘膜的顶表面上，其中所述互连衬底包括由所述第一互连形成的第一互连图案，所述第一互连图案至少包括沿着与第一互连正交的第二方向延伸的线状图案 第一方向和翘曲控制图案，其设置在基底绝缘膜的底面的下沉部分中，并且形成为抑制互连基板朝向底部绝缘膜两侧的底侧的翘曲 第一个方向