公开(公告)号：US20180096962A1

公开(公告)日：2018-04-05

申请号：US15820907

申请日：2017-11-22

Applicant: EV Group E. Thallner GmbH

Inventor： Andreas Fehkuhrer

IPC: H01L23/00 ,  H01L25/00 ,  B32B37/00 ,  H01L23/544 ,  H01L21/683 ,  H01L21/67 ,  H01L21/304 ,  H01L21/18 ,  B32B38/18 ,  H01L25/065 ,  H01L21/78

CPC classification number: H01L24/80 ,  B32B37/0046 ,  B32B38/1841 ,  B32B38/1858 ,  B32B2309/105 ,  B32B2457/14 ,  H01L21/187 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/08 ,  H01L24/74 ,  H01L24/75 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/0224 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/75251 ,  H01L2224/75272 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/80 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80047 ,  H01L2224/80051 ,  H01L2224/80093 ,  H01L2224/80099 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80209 ,  H01L2224/80213 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2221/68304

Abstract: A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

公开(公告)号：US20170358551A1

公开(公告)日：2017-12-14

申请号：US15689982

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

公开(公告)号：US09842785B2

公开(公告)日：2017-12-12

申请号：US15333098

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC: H01L21/66 ,  H01L23/492 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L22/34 ,  H01L21/768 ,  H01L22/20 ,  H01L22/30 ,  H01L23/492 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L24/94 ,  H01L2224/0237 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.

公开(公告)号：US09748198B2

公开(公告)日：2017-08-29

申请号：US14725266

申请日：2015-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  H01L21/46 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

公开(公告)号：US20170213746A1

公开(公告)日：2017-07-27

申请号：US15482346

申请日：2017-04-07

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Yuankun HOU ,  Kuanchieh YU ,  Yu HUA ,  Yuelin ZHAO

IPC: H01L21/56 ,  H01L21/308 ,  H01L23/10 ,  H01L21/306 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/56 ,  H01L21/30604 ,  H01L21/308 ,  H01L22/12 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05571 ,  H01L2224/0612 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29078 ,  H01L2224/30145 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/80011 ,  H01L2224/80203 ,  H01L2224/80805 ,  H01L2224/8081 ,  H01L2224/80895 ,  H01L2224/83011 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8381 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/163 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/2919 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80

Abstract: A method of forming a sealing structure for a bonded wafer is provided. The method includes providing the lower wafer and the upper wafer, forming a sealing material layer on each of the lower wafer and the upper wafer, forming a mask layer on the sealing material layer on each of the lower wafer and the upper wafer, etching the sealing material layer using the mask layer as an etch mask, so as to form a first protrusion at an edge of the lower wafer and a second protrusion at an edge of the upper wafer, and bonding the first protrusion and the second protrusion together to form the sealing structure. The sealing structure encloses a gap between the lower wafer and the upper wafer at an edge of the bonded wafer, so as to form a hermetically sealed cavity at the edge of the bonded wafer.

公开(公告)号：US09646860B2

公开(公告)日：2017-05-09

申请号：US13963741

申请日：2013-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Xiaomeng Chen ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC: H01L21/68 ,  H01L21/67 ,  H01L23/00

CPC classification number: H01L24/94 ,  H01L21/67092 ,  H01L21/681 ,  H01L24/08 ,  H01L24/74 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00015 ,  H01L2224/80121 ,  H01L2924/00

Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.

公开(公告)号：US20160358882A1

公开(公告)日：2016-12-08

申请号：US15238532

申请日：2016-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Lan-Lin Chao ,  Cheng-Tai Hsiao ,  Xin-Hua Huang ,  Hsun-Chung Kuang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/80 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/89 ,  H01L25/0657 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/0516 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/8084 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/8192 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001

Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.

公开(公告)号：US09443802B2

公开(公告)日：2016-09-13

申请号：US14718942

申请日：2015-05-21

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Kenichi Aoyagi ,  Yoshiya Hagimoto ,  Nobutoshi Fujii

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L27/146 ,  H01L23/00 ,  H04N5/369 ,  H01L23/532 ,  H01L27/06

CPC classification number: H01L27/14636 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L27/0688 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2221/1031 ,  H01L2224/02245 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80091 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83345 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/13091 ,  H04N5/369 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

公开(公告)号：US20160251495A1

公开(公告)日：2016-09-01

申请号：US15148320

申请日：2016-05-06

Applicant: Alpha Metals, Inc.

Inventor： Rajan Hariharan ,  James Hurley ,  Senthil Kanagavel ,  Jose Quinones ,  Martin Sobczak ,  Deborah Makita

IPC: C08K5/09 ,  C08K3/08 ,  H01L23/31 ,  H01L23/00 ,  H01L23/04

CPC classification number: C08K5/09 ,  B23K35/3612 ,  B23K2101/36 ,  C08K3/08 ,  C08K2003/0806 ,  C08K2003/0837 ,  C08K2003/085 ,  H01B1/22 ,  H01L23/04 ,  H01L23/3178 ,  H01L23/4928 ,  H01L23/49883 ,  H01L24/80 ,  H01L2224/03332 ,  H01L2224/03442 ,  H01L2224/80011 ,  H01L2924/0002 ,  H05K7/02 ,  H01L2924/00

Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

Abstract translation: 导电组合物包括单酸混合物，其包含未被保护的单个反应性基团。 单酸杂化物可以在其他地方包括基本上非反应性基团，使得单酸杂合物作为链终止剂起作用。 还公开了使用该组合物的方法和装置。

公开(公告)号：US09355938B2

公开(公告)日：2016-05-31

申请号：US14058553

申请日：2013-10-21

Applicant: ALPHA METALS, INC.

Inventor： Rajan Hariharan ,  James Hurley ,  Senthil Kanagavel ,  Jose Quinones ,  Martin Sobczak ,  Deborah Makita

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K5/00 ,  H05K7/00 ,  H01B1/02 ,  H01B1/22 ,  C09K5/00 ,  H01L23/492 ,  B23K35/36 ,  H01L23/498 ,  H05K7/02 ,  C08K5/09

CPC classification number: C08K5/09 ,  B23K35/3612 ,  B23K2101/36 ,  C08K3/08 ,  C08K2003/0806 ,  C08K2003/0837 ,  C08K2003/085 ,  H01B1/22 ,  H01L23/04 ,  H01L23/3178 ,  H01L23/4928 ,  H01L23/49883 ,  H01L24/80 ,  H01L2224/03332 ,  H01L2224/03442 ,  H01L2224/80011 ,  H01L2924/0002 ,  H05K7/02 ,  H01L2924/00

Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

Abstract translation: 导电组合物包括单酸混合物，其包含未被保护的单个反应性基团。 单酸杂化物可以在其他地方包括基本上非反应性基团，使得单酸杂合物作为链终止剂起作用。 还公开了使用该组合物的方法和装置。