公开(公告)号：US09960088B2

公开(公告)日：2018-05-01

申请号：US13290879

申请日：2011-11-07

申请人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B24B49/10 ,  H01L21/66 ,  B24B37/013 ,  B24B7/22 ,  H01L23/31

CPC分类号： H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

公开(公告)号：US09536818B2

公开(公告)日：2017-01-03

申请号：US13272434

申请日：2011-10-13

申请人： Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L23/498 ,  B23K1/20 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49894 ,  H01L21/4864 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

摘要： A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.

摘要翻译： 半导体封装的方法包括提供具有涂覆有有机可焊性防腐剂（OSP）层的导电迹线的衬底，从导电迹线去除OSP层，然后将芯片耦合到衬底以形成半导体封装。

公开(公告)号：US09443783B2

公开(公告)日：2016-09-13

申请号：US13619877

申请日：2012-09-14

申请人： Jing-Cheng Lin ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chen-Hua Yu

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/03 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14144 ,  H01L2224/14154 ,  H01L2224/14164 ,  H01L2224/14181 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665

摘要： A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

摘要翻译： 提供了一种三维堆叠半导体器件的系统和方法。 在一个实施例中，将两个或更多个半导体管芯附着到载体并封装。 两个或更多个半导体管芯的连接被暴露，并且两个或更多个半导体管芯可以被薄化以在相对侧上形成连接。 然后可以将另外的半导体管芯置于偏移或悬垂位置中。

公开(公告)号：US09257506B2

公开(公告)日：2016-02-09

申请号：US13179275

申请日：2011-07-08

申请人： Ding-Yuan Chen ,  Chen-Hua Yu

发明人： Ding-Yuan Chen ,  Chen-Hua Yu

IPC分类号： H01L27/088 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric.

公开(公告)号：US09224606B2

公开(公告)日：2015-12-29

申请号：US13336887

申请日：2011-12-23

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76202 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

摘要翻译： 包括可折入隔离结构的半导体器件和用于制造这种器件的方法。 优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。 至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。 在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

公开(公告)号：US09209157B2

公开(公告)日：2015-12-08

申请号：US13074883

申请日：2011-03-29

申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

IPC分类号： H01L21/44 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

公开(公告)号：US09165875B2

公开(公告)日：2015-10-20

申请号：US13456038

申请日：2012-04-25

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Kai-Chiang Wu

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Kai-Chiang Wu

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/13017 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate.

摘要翻译： 插入器包括具有接触焊盘结构的基板和可操作地耦合到接触垫结构的螺柱。 焊球位于接触垫结构上并形成在螺柱周围。 螺柱被配置为当顶部封装安装到基板时调节焊球的塌陷。

公开(公告)号：US09123553B2

公开(公告)日：2015-09-01

申请号：US13269260

申请日：2011-10-07

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Yuh-Jier Mii ,  Yuan-Chen Sun

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Yuh-Jier Mii ,  Yuan-Chen Sun

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L21/50 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/762 ,  H01L21/76898 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.

摘要翻译： 一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。 该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。 与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中的一种或多种。 在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。 在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

公开(公告)号：US09024431B2

公开(公告)日：2015-05-05

申请号：US12846214

申请日：2010-07-29

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L23/00

CPC分类号： H01L23/528 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

摘要翻译： 公开了一种用于形成半导体管芯接触结构的系统和方法。 一个实施例包括顶层金属接触，例如铜，其厚度足够大以充当底层低k，极低k或超低k电介质层的缓冲器。 可以在顶层金属接触件上方形成接触焊盘或后钝化互连，并且可以形成铜柱或焊料凸块以与顶层金属接触件电连接。

公开(公告)号：US09010617B2

公开(公告)日：2015-04-21

申请号：US12987702

申请日：2011-01-10

申请人： Chen-Hua Yu ,  Wen-Yao Chang ,  Chien Rhone Wang ,  Kewei Zuo ,  Chung-Shi Liu

发明人： Chen-Hua Yu ,  Wen-Yao Chang ,  Chien Rhone Wang ,  Kewei Zuo ,  Chung-Shi Liu

IPC分类号： B23K31/02 ,  H01L21/44 ,  H01L23/00

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/75 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/81055 ,  H01L2224/81097 ,  H01L2224/81098 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81805 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13139

摘要： In a reflow process, a plurality of solder bumps between a first workpiece and a second workpiece is melted. During a solidification stage of the plurality of solder bumps, the plurality of solder bumps is cooled at a first cooling rate. After the solidification stage is finished, the plurality of solder bumps is cooled at a second cooling rate lower than the first cooling rate.

摘要翻译： 在回流工艺中，第一工件和第二工件之间的多个焊料凸块熔化。 在多个焊料凸块的凝固阶段期间，以第一冷却速度冷却多个焊料凸块。 凝固阶段结束后，以比第一冷却速度低的第二冷却速度冷却多个焊锡凸块。