公开(公告)号：US08629059B2

公开(公告)日：2014-01-14

申请号：US12969977

申请日：2010-12-16

申请人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

发明人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20110104888A1

公开(公告)日：2011-05-05

申请号：US12797837

申请日：2010-06-10

申请人： Ki-Hyuk KIM ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

发明人： Ki-Hyuk KIM ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

IPC分类号： H01L21/768

CPC分类号： H01L21/76813 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

摘要翻译： 半导体器件及其形成方法，包括在芯片衬底上形成芯片焊盘，在芯片焊盘和芯片衬底上形成钝化层，在钝化层上形成第一绝缘层，形成凹槽和第一开口 所述第一绝缘层在所述钝化层中形成对应于所述第一开口的第二开口，在所述凹部，所述第一开口和所述第二开口的再分布线区域中形成再分配线，在所述再分布上形成第二绝缘层 线和第一绝缘层，并且在第二绝缘体中形成开口以将再分配线的一部分暴露为再分布焊盘。

公开(公告)号：US20100190333A1

公开(公告)日：2010-07-29

申请号：US12691780

申请日：2010-01-22

申请人： Myeong-Soon PARK ,  Eunchul Ahn ,  Hyunsoo Chung ,  Seokho Kim ,  Do-Yeon Choi ,  Jinho Chun

发明人： Myeong-Soon PARK ,  Eunchul Ahn ,  Hyunsoo Chung ,  Seokho Kim ,  Do-Yeon Choi ,  Jinho Chun

IPC分类号： H01L21/60

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion.

摘要翻译： 形成连接端子的方法可以包括：准备衬底，在衬底上形成具有开口上部的管状第一导体，在第一导体上形成第二导体，并使第二导体退火， 第二导体通过开口的上部在第一导体的内部空间中延伸。

公开(公告)号：US20090230548A1

公开(公告)日：2009-09-17

申请号：US12193835

申请日：2008-08-19

申请人： Myeong-soon PARK ,  Hyun-soo CHUNG ,  Seok-ho KIM ,  Ki-hyuk KIM ,  Chang-woo SHIN

发明人： Myeong-soon PARK ,  Hyun-soo CHUNG ,  Seok-ho KIM ,  Ki-hyuk KIM ,  Chang-woo SHIN

IPC分类号： H01L23/49

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/731 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip.

摘要翻译： 半导体封装可以具有半导体芯片，其包括形成在包括集成电路的基板上的芯片焊盘和暴露芯片焊盘的钝化层，连接到芯片焊盘并在半导体芯片上延伸的第一再分配布线层，以及 包括用于提供引线接合的引线接合焊盘和将第一再分配布线层连接到第二半导体芯片的第一焊盘，以及连接到第一再分布布线层上的第一再分布布线层的第二再分布布线层， 第二焊盘，用于将第二再分配布线层连接到第三半导体芯片。

公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20060038291A1

公开(公告)日：2006-02-23

申请号：US11080956

申请日：2005-03-16

申请人： Hyun-soo Chung ,  Sung-min Sim ,  Myeong-soon Park ,  Dong-hyeon Jang ,  Young-hee Song

发明人： Hyun-soo Chung ,  Sung-min Sim ,  Myeong-soon Park ,  Dong-hyeon Jang ,  Young-hee Song

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H05K3/0023 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： In the manufacture of a semiconductor device, a photosensitive layer is deposited to cover an exposed portion of an electrode with the photosensitive layer. The photosensitive layer is then subjected to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode may be a ball electrode or a bump electrode, and the semiconductor device may be contained in a wafer level package (WLP) or flip-chip package.

摘要翻译： 在半导体器件的制造中，沉积感光层以覆盖具有感光层的电极的暴露部分。 然后对感光层进行光刻处理，以部分去除覆盖电极的感光层。 电极可以是球形电极或凸块电极，并且半导体器件可以包含在晶片级封装（WLP）或倒装芯片封装中。

公开(公告)号：US20160351472A1

公开(公告)日：2016-12-01

申请号：US15053410

申请日：2016-02-25

申请人： MYEONG-SOON PARK ,  HYUN-SOO CHUNG ,  CHAN-HO LEE

发明人： MYEONG-SOON PARK ,  HYUN-SOO CHUNG ,  CHAN-HO LEE

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/03462 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure. A conductive pad is disposed on a second surface, opposite to the first surface, of the semiconductor structure. A through-substrate-via (TSV) structure penetrates through the semiconductor structure. An end portion of the TSV structure extends beyond the second surface of the semiconductor structure. The conductive pad surrounds the end portion of the TSV structure. The connection terminal is electrically connected to the conductive pad through the TSV structure

摘要翻译： 如下提供集成电路器件。 连接端子设置在半导体结构的第一表面上。 导电焊盘设置在半导体结构的与第一表面相对的第二表面上。 贯穿衬底通孔（TSV）结构穿透半导体结构。 TSV结构的端部延伸超过半导体结构的第二表面。 导电焊盘围绕TSV结构的端部。 连接端子通过TSV结构电连接到导电焊盘

公开(公告)号：US20140124901A1

公开(公告)日：2014-05-08

申请号：US14153478

申请日：2014-01-13

申请人： Ho-jin Lee ,  Kang-wook Lee ,  Myeong-soon Park ,  Ju-iI Choi ,  Son-kwan Hwang

发明人： Ho-jin Lee ,  Kang-wook Lee ,  Myeong-soon Park ,  Ju-iI Choi ,  Son-kwan Hwang

IPC分类号： H01L23/528 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US08431479B2

公开(公告)日：2013-04-30

申请号：US12797837

申请日：2010-06-10

申请人： Ki-Hyuk Kim ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

发明人： Ki-Hyuk Kim ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76813 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

摘要翻译： 半导体器件及其形成方法，包括在芯片衬底上形成芯片焊盘，在芯片焊盘和芯片衬底上形成钝化层，在钝化层上形成第一绝缘层，形成凹槽和第一开口 所述第一绝缘层在所述钝化层中形成对应于所述第一开口的第二开口，在所述凹部，所述第一开口和所述第二开口的再分布线区域中形成再分配线，在所述再分布上形成第二绝缘层 线和第一绝缘层，并且在第二绝缘体中形成开口以将再分配线的一部分暴露为再分布焊盘。

公开(公告)号：US07875552B2

公开(公告)日：2011-01-25

申请号：US12476793

申请日：2009-06-02

申请人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

发明人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。