公开(公告)号：US20130042472A1

公开(公告)日：2013-02-21

申请号：US13617694

申请日：2012-09-14

申请人： Doo-Hwan LEE ,  Byoung-Youl MIN ,  Myung-Sam KANG ,  Moon-II KIM ,  Hyung-Tae KIM

发明人： Doo-Hwan LEE ,  Byoung-Youl MIN ,  Myung-Sam KANG ,  Moon-II KIM ,  Hyung-Tae KIM

IPC分类号： H05K3/30

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/056 ,  H05K3/4608 ,  H05K2201/10515 ,  Y10T29/4913 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A method of manufacturing a printed circuit board having embedded electronic components, the method including: mounting a first electronic component on one side of a core sheet and mounting a second electric component on the other side of the core sheet such that the second electronic component overlaps the first electronic component; stacking a first insulation layer on one side of the core sheet such that the first insulation layer covers the first electronic component and stacking a second insulation layer on the other side of the core sheet such that the second insulation layer covers the second electronic component; and forming a circuit pattern on a surface of the first insulation layer or the second insulation layer.

摘要翻译： 一种制造具有嵌入式电子部件的印刷电路板的方法，所述方法包括：将第一电子部件安装在芯片的一侧，并将第二电气部件安装在芯板的另一侧，使得第二电子部件重叠 第一个电子元件; 在芯片的一侧堆叠第一绝缘层，使得第一绝缘层覆盖第一电子部件，并且在芯片的另一侧堆叠第二绝缘层，使得第二绝缘层覆盖第二电子部件; 以及在所述第一绝缘层或所述第二绝缘层的表面上形成电路图案。

公开(公告)号：US20120088334A1

公开(公告)日：2012-04-12

申请号：US13007444

申请日：2011-01-14

申请人： Mi Sun HWANG ,  Keung Jin SOHN ,  Eung Suek LEE ,  Myung Sam KANG

发明人： Mi Sun HWANG ,  Keung Jin SOHN ,  Eung Suek LEE ,  Myung Sam KANG

IPC分类号： H01L21/60

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2203/0384 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed herein is a method for manufacturing a semiconductor package which uses a base member 120 in which a first metal layer 113, a barrier layer 115, and a second metal layer 117 are stacked on both surface thereof in sequence based on an adhesive member 111 to simultaneously manufacture two printed circuit boards through a single sheet process, thereby making it possible to improve manufacturing efficiency; electrically connects a semiconductor chip 300 to a printed circuit board through a solder bump 250, thereby making it possible to implement a high-density package substrate; and forms a metal post 140 instead of a through hole to required in an interlayer circuit connection, thereby making it possible to reduce costs required in the processing/plating of the through hole.

摘要翻译： 本发明公开了一种半导体封装件的制造方法，该半导体封装件使用基片120，其中第一金属层113，阻挡层115和第二金属层117依次以两个表面层叠在第一金属层113，阻挡层115和第二金属层117上， 同时通过单片工艺制造两个印刷电路板，从而可以提高制造效率; 通过焊料凸块250将半导体芯片300电连接到印刷电路板，从而可以实现高密度封装基板; 并且形成金属柱140而不是层间电路连接所需的通孔，从而可以降低通孔的加工/电镀所需的成本。

公开(公告)号：US08141241B2

公开(公告)日：2012-03-27

申请号：US12379684

申请日：2009-02-26

申请人： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

发明人： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC分类号： H01R9/00 ,  H01R43/16 ,  H01R43/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/10 ,  H05K1/11

CPC分类号： H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

摘要： A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a metal carrier; forming a barrier layer on the metal carrier including the recess; forming an upper circuit layer on the barrier layer, the upper circuit layer including the metal bump charged in the recess and a circuit pattern; preparing an insulating layer, and transferring the upper circuit layer to the insulating layer; and removing the metal carrier and the barrier layer.

摘要翻译： 一种制造具有金属凸块的印刷电路板的方法，包括：在金属载体上形成用于形成金属凸块的凹槽; 在包括所述凹部的所述金属载体上形成阻挡层; 在所述阻挡层上形成上层电路层，所述上层电路层包括填充在所述凹部中的所述金属凸块和电路图案; 制备绝缘层，并将上电路层转移到绝缘层; 并移除金属载体和阻挡层。

公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/03

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

摘要翻译： 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20110318480A1

公开(公告)日：2011-12-29

申请号：US13137631

申请日：2011-08-30

申请人： Ki Hwan Kim ,  Jin Yong An ,  Myung Sam Kang

发明人： Ki Hwan Kim ,  Jin Yong An ,  Myung Sam Kang

IPC分类号： H05K3/00

CPC分类号： H05K3/0097 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2203/0156 ,  H05K2203/1536

摘要： A method of manufacturing a substrate using a carrier, that includes preparing a carrier having a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; patterning the metal layers to form base circuit layers; forming buildup layers on the base circuit layers; executing a routing process to separate the insulating layers from the releasing layer; and forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.

摘要翻译： 使用载体制造衬底的方法，其包括制备具有释放层的载体，以及顺序地设置在释放层两侧的绝缘层和金属层; 图案化金属层以形成基极电路层; 在基极电路层上形成积层; 执行布线过程以将绝缘层与释放层分离; 以及在堆积层上形成阻焊层，并在阻焊层和绝缘层中形成开口以露出焊盘。

公开(公告)号：US20110221074A1

公开(公告)日：2011-09-15

申请号：US13067219

申请日：2011-05-17

申请人： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

发明人： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC分类号： H01L23/488

CPC分类号： H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip.

摘要翻译： 一种片上封装，包括具有空腔和一侧图案的光阻焊剂，该图案对应于电路线; 容纳在腔中的焊球垫; 与焊锡球焊盘电连接并形成在光阻焊剂的另一侧上的电路线; 通过倒装芯片焊接安装在焊球垫上的半导体芯片; 以及用于模制半导体芯片的钝化材料。

公开(公告)号：US20110163823A1

公开(公告)日：2011-07-07

申请号：US12983073

申请日：2010-12-31

申请人： Dae-Hyun PARK ,  Han Kim ,  Myung-Sam Kang

发明人： Dae-Hyun PARK ,  Han Kim ,  Myung-Sam Kang

IPC分类号： H04B3/28

CPC分类号： H05K1/0236 ,  H05K1/165 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/097

摘要： In an electromagnetic bandgap structure including a plurality of conductive plates and a stitching via part, in which the plurality of conductive plates are placed on a first planar surface, the stitching via part includes a first via having one end part connected to one of the two conductive plates, a second via having one end part connected to the other of the two conductive plates, a spiral connector forming a spirally-shaped serial link structure on at least one vertical planar surface that is perpendicular to the first planar surface, a first conductive pattern connecting one end part of the spiral connector and the other end part of the first via with each other and a second conductive connecting pattern connecting the other end part of the spiral connector and the other end part of the second via with each other.

摘要翻译： 在包括多个导电板和缝合通孔部分的电磁带隙结构中，其中多个导电板被放置在第一平坦表面上，该缝合通孔部分包括第一通孔，该第一通孔的一个端部连接到两个 导电板，具有连接到两个导电板中的另一个的一个端部的第二通孔，在垂直于第一平坦表面的至少一个垂直平面上形成螺旋形串联结构的螺旋形连接器，第一导电 螺旋连接器的一个端部和第一通孔的另一个端部彼此连接的图案，以及将螺旋形连接器的另一个端部和第二通孔的另一个端部彼此连接的第二导电连接图案。

公开(公告)号：US20110095425A1

公开(公告)日：2011-04-28

申请号：US12923037

申请日：2010-08-30

申请人： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

发明人： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L21/50

CPC分类号： H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

摘要翻译： 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。

公开(公告)号：US20110061906A1

公开(公告)日：2011-03-17

申请号：US12654433

申请日：2009-12-18

申请人： Min Jung Cho ,  Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

发明人： Min Jung Cho ,  Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

IPC分类号： H05K1/09 ,  B05D5/12

CPC分类号： H05K1/0271 ,  H05K1/09 ,  H05K3/007 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/10674

摘要： A printed circuit board (PCB) and a fabrication method thereof are disclosed. The PCB includes: a dual-layered circuit pattern formed with a desired pattern on at least one of upper and lower surfaces of an insulation base member (i.e., an insulation substrate) and having metal layers each having a different thermal expansion coefficient; and an insulating layer formed on the insulation base member to cover the circuit pattern. Because the PCB includes an anti-warping unit, a processing rate and productivity can be improved.

摘要翻译： 公开了印刷电路板（PCB）及其制造方法。 PCB包括：在绝缘基底（即绝缘基板）的上表面和下表面的至少一个表面上形成具有期望图案并且具有各自具有不同热膨胀系数的金属层的双层电路图案; 以及形成在所述绝缘基底构件上以覆盖所述电路图案的绝缘层。 由于PCB包括抗翘曲单元，因此可以提高加工速度和生产率。

公开(公告)号：US20110061231A1

公开(公告)日：2011-03-17

申请号：US12631594

申请日：2009-12-04

申请人： Mi Sun HWANG ,  Myung Sam KANG ,  Ok Tae KIM ,  Seon Ha KANG ,  Gil Yong SHIN ,  Kil Yong YUN ,  Min Jung CHO

发明人： Mi Sun HWANG ,  Myung Sam KANG ,  Ok Tae KIM ,  Seon Ha KANG ,  Gil Yong SHIN ,  Kil Yong YUN ,  Min Jung CHO

IPC分类号： H05K3/36 ,  H05K3/10

CPC分类号： H05K3/4685 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.

摘要翻译： 本文公开了一种制造印刷电路板的方法，包括：制备第一载体，其包括在其一侧上形成的第一图案; 制备包括在其一侧上顺序形成的第一阻焊层和第二图案的第二载体; 按压第一载体和第二载体，使得第一图案嵌入绝缘层的一侧，并且将第二图案嵌入绝缘层的另一侧，然后移除第一载体和第二载体以制造两个基板 ; 使用粘合层将两个基板彼此连接，使得第一阻焊层彼此面对; 以及形成用于在绝缘层中连接第一图案与第二图案的通孔，在设置有第一图案的绝缘层上形成第二阻焊剂，然后除去粘合层。