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    Multilayer interconnect structure containing air gaps and method for making
    1.
    发明申请
    Multilayer interconnect structure containing air gaps and method for making 有权
    包含气隙的多层互连结构和制造方法

    公开(公告)号：US20070259516A1

    公开(公告)日：2007-11-08

    申请号：US11429708

    申请日：2006-05-08

    申请人： Christopher Jahnes ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Katherine Saenger

    发明人： Christopher Jahnes ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Katherine Saenger

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive vias embedded in one or more dielectric layers in which the dielectric layers are solid underneath and above line features in adjacent levels, and perforated between line features. The line levels contain conductive lines and an air-gap-containing dielectric. A solid dielectric bridge layer, containing conductive contacts and formed by filling in a perforated dielectric layer, is disposed over the collection of interspersed line and via levels.

    摘要翻译： 提供了一种具有多级气隙的互连结构及其制造方法。 多层含气隙的互连结构包括散布的线电平和通孔电平的集合，其中通孔层包括嵌入在一个或多个电介质层中的导电通孔，其中电介质层在相邻电平之下的电极特征和固定电极层之上，以及 线之间穿孔特征。 线路电平包含导电线和含气隙的电介质。 包含导电接触并通过填充有孔电介质层形成的固体介质桥接层设置在散布的线路和通孔层的集合上。

    METHOD TO CREATE REGION SPECIFIC EXPOSURE IN A LAYER
    2.
    发明申请
    METHOD TO CREATE REGION SPECIFIC EXPOSURE IN A LAYER 有权
    创建区域特定暴露的方法

    公开(公告)号：US20060183062A1

    公开(公告)日：2006-08-17

    申请号：US10906268

    申请日：2005-02-11

    申请人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

    发明人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nitta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

    IPC分类号： G03F7/00

    CPC分类号： G03F7/2022

    摘要： A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

    摘要翻译： 提供了一种在邻接区域中对材料性质进行不同的改变的同时选择性地改变一个区域中的衬底的材料特性的方法。 该方法包括在第一曝光期间选择性地掩蔽衬底的第一部分，并且在第二次曝光期间选择性地掩蔽衬底的第二部分。 另外，可以形成具有多于一个厚度的掩模，其中每个厚度将选择性地减少来自衬底的覆盖曝光的能量的量，从而允许衬底在单次覆盖曝光中接收不同水平的能量。

    SELF-ALIGNED CONTACT
    6.
    发明申请
    SELF-ALIGNED CONTACT 有权
    自对准联系人

    公开(公告)号：US20100210098A1

    公开(公告)日：2010-08-19

    申请号：US12372174

    申请日：2009-02-17

    申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

    发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

    摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

    摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。