公开(公告)号：US06512675B1

公开(公告)日：2003-01-28

申请号：US09764132

申请日：2001-01-19

申请人： Thomas S. Tarter ,  Eric S. Tosaya ,  Tom J. Ley ,  Shrikar Bhagath ,  Nhon T. Do

发明人： Thomas S. Tarter ,  Eric S. Tosaya ,  Tom J. Ley ,  Shrikar Bhagath ,  Nhon T. Do

IPC分类号： H05K720

CPC分类号： H01L23/3675 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： An intregrated circuit package, which has an intregrated circuit die thereto, is mounted to a system board. The ground trace of the system board is connected to the package, which has a pluality of ground leads on its surface. An electrically conductive epoxy is placed on the ground leads and adheres the package lid to the package board and ground the package lid. A heat sink is mounted to the package lid with an electrically conductive adhesive or electrically conductive slips that extend from a flange of the package lid to a flange of the heat sink to ground the heat sink.

摘要翻译： 具有集成电路的集成电路封装被安装到系统板上。 系统板的接地线连接到封装，其表面具有接地引线。 将导电环氧树脂放置在接地引线上，并将封装盖粘合到封装板上并将封装盖接地。 散热器通过导电粘合剂或导电滑块安装到封装盖上，导电滑块从封装盖的凸缘延伸到散热器的凸缘以将散热器接地。

公开(公告)号：US08637978B2

公开(公告)日：2014-01-28

申请号：US13235781

申请日：2011-09-19

申请人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

发明人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

IPC分类号： H01L23/12 ,  H01L23/02

CPC分类号： G06K19/07745 ,  G06K19/07732 ,  G11C5/04 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/0052 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

公开(公告)号：US20080128879A1

公开(公告)日：2008-06-05

申请号：US11679094

申请日：2007-02-26

申请人： Hem Takiar ,  Shrikar Bhagath ,  Chin-Tien Chiu ,  Ong King Hoo

发明人： Hem Takiar ,  Shrikar Bhagath ,  Chin-Tien Chiu ,  Ong King Hoo

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85186 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer in which the wire bond loops from the first semiconductor die are embedded. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. A dielectric layer may be formed on a back surface of the second semiconductor die. As the back side of the second semiconductor die is an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The intermediate layer may thus be made thinner in comparison to conventional stacked semiconductor die configurations.

摘要翻译： 公开了一种低剖面半导体封装，其包括至少安装到衬底的第一和第二层叠半导体管芯。 第一半导体管芯和第二半导体管芯由嵌入第一半导体管芯的引线接合环路的低剖面中间粘合剂层分开。 在施加中间层之后，第二半导体管芯可以堆叠在中间层的顶部上。 可以在第二半导体管芯的后表面上形成电介质层。 由于第二半导体管芯的背面是电绝缘体，所以如现有技术那样，中间层不需要与第二半导体管芯的引线接合环空间，并且接合线的顶点可能与介电层接触。 因此，与传统的堆叠半导体管芯配置相比，中间层可以被制成更薄。

公开(公告)号：US20070004094A1

公开(公告)日：2007-01-04

申请号：US11171095

申请日：2005-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

IPC分类号： H01L21/58

CPC分类号： H01L23/49855 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0271 ,  H05K2201/09681 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

摘要翻译： 公开了用于半导体封装的衬底的表面上的虚拟电路图案，该虚拟电路图案包括直线段，其长度受到控制，以便不在所述线段内产生高于所需应力的应力。 虚拟电路图案可以由线或邻接的或间隔开的多边形（例如六边形）形成。 虚拟电路图案的部分也可以形成为随机选择的取向，尺寸和位置。

公开(公告)号：US20060267173A1

公开(公告)日：2006-11-30

申请号：US11140608

申请日：2005-05-26

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Ming Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Ming Wang

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.

摘要翻译： 公开了用于在集成电路封装内堆叠集成电路管芯的改进的技术。 这些改进的技术允许集成电路封装内的集成电路管芯的堆叠密度更高。 此外，改进的堆叠技术允许用于将各种集成电路管芯彼此或与衬底电连接的常规焊接技术。 这些改进的方法对于在集成电路封装内堆叠相同尺寸（并且通常是相同功能的）集成电路管芯特别有用。 这种集成电路封装的一个例子是非易失性存储器集成电路封装，其包含堆叠地布置的多个相同大小的存储器集成电路管芯。

公开(公告)号：US08575724B2

公开(公告)日：2013-11-05

申请号：US12906523

申请日：2010-10-18

申请人： Shrikar Bhagath ,  Hem Takiar

发明人： Shrikar Bhagath ,  Hem Takiar

IPC分类号： H01L23/492

CPC分类号： H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

摘要翻译： 一种半导体器件，其包括在被填充有薄膜的裸片堆叠中的半导体管芯。 一旦半导体管芯形成，它们可以被堆叠和互连。 互连可能在芯片堆叠中的半导体管芯之间留下小的空间。 该空间有利地使用气相沉积工艺完全填充，其中涂层作为蒸汽沉积，该蒸汽流过管芯堆叠的所有表面，包括进入堆叠中的管芯之间的空间。 然后，蒸汽沉积在模具之间和周围的表面上并形成完全填充模具堆叠中的模具之间的空间的膜。 在气相沉积填充过程中使用的材料可以例如是聚对二甲苯聚合物族的成员，并且在实施方案中可以是聚对二甲苯-N。

公开(公告)号：US08470640B2

公开(公告)日：2013-06-25

申请号：US12165297

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

发明人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

IPC分类号： H01L21/00

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04953 ,  H01L2924/078 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

摘要翻译： 公开了半导体管芯和低剖面半导体封装的制造方法。 半导体封装可以包括安装到衬底的至少第一和第二堆叠半导体管芯。 第一和/或第二半导体管芯可以沿着半导体管芯的侧边缘通过半导体管芯的底表面被制造成具有局部空腔。 一个侧面中的一个或多个局部空腔占据整个侧面。 因此，局部空腔允许半导体芯片的低高度堆叠，同时为每个模具提供高度的结构完整性，以防止在制造期间模头边缘的破裂或断裂。

公开(公告)号：US20120279651A1

公开(公告)日：2012-11-08

申请号：US13257285

申请日：2011-05-05

申请人： Wei Gu ,  Zhong Lu ,  Shrikar Bhagath ,  Chin-Tien Chiu ,  Hem Takiar ,  XiangYang Liu

发明人： Wei Gu ,  Zhong Lu ,  Shrikar Bhagath ,  Chin-Tien Chiu ,  Hem Takiar ,  XiangYang Liu

IPC分类号： H01L21/64 ,  B05C11/00 ,  B32B3/10 ,  B05D5/10 ,  C09J7/02 ,  B05C21/00 ,  B05B1/00

CPC分类号： H01L24/83 ,  B05B12/20 ,  B05B13/02 ,  B05B14/00 ,  H01L21/56 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/743 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29034 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1438 ,  H01L2924/181 ,  Y10T156/1092 ,  Y10T428/24802 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system and method are disclosed for applying a die attach epoxy to substrates on a panel of substrates. The system includes a window clamp having one or more windows through which the epoxy may be applied onto the substrate panel. The size and shape of the one or more windows correspond to the size and shape of the area on the substrate to receive the die attach epoxy. Once the die attach epoxy is sprayed onto the substrate through the windows of the window clamp, the die may be affixed to the substrate and the epoxy cured in one or more curing steps. The system may further include a clean-up follower for cleaning epoxy off of the window clamp, and a window cleaning mechanism for cleaning epoxy off of the sidewalls of the windows of the window clamp.

摘要翻译： 公开了一种用于将芯片附着环氧树脂施加到基板面板上的基板的系统和方法。 该系统包括具有一个或多个窗口的窗口夹具，环氧树脂可以通过该窗口施加到基板面板上。 一个或多个窗口的尺寸和形状对应于基板上的区域的尺寸和形状以接收管芯附着环氧树脂。 一旦模具附着环氧树脂通过窗口夹具的窗口喷涂到基材上，模具可以固定在基材上，环氧树脂在一个或多个固化步骤中固化。 该系统还可以包括用于清洁窗夹的环氧树脂的清理跟随器，以及用于从窗夹的窗口侧壁清洁环氧树脂的窗清洁机构。

公开(公告)号：US08241953B2

公开(公告)日：2012-08-14

申请号：US12165340

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L21/00

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/01047 ,  H01L2224/85186 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00015

摘要： A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

摘要翻译： 公开了一种制造低轮廓半导体封装件的方法，该方法至少包括安装到衬底上的第一和第二层叠半导体管芯。 第一和/或第二半导体管芯可以被制造成多个再分配焊盘，其形成在多个接合焊盘上并电耦合到多个接合焊盘。 在半导体管芯从晶片形成和切割之后，可以使用根据本发明的低剖面反向引线接合将管芯安装到衬底上。 特别地，在传统的反向接合工艺中，可以在导线和再分布垫之间形成楔形键，而不必在芯片接合焊盘上使用第二线接合球。

公开(公告)号：US07795715B2

公开(公告)日：2010-09-14

申请号：US12363311

申请日：2009-01-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/02

CPC分类号： H01L23/49541 ,  G06K19/07732 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.

摘要翻译： 公开了一种用于形成具有曲线形状的引线框半导体封装的引线框设计。 引线框可以各自包括对应于精加工和分割半导体封装中的曲线边缘的一个或多个曲线槽。 在封装之后，面板上的集成电路封装可以通过将集成电路从引线框板切割成多个单独的集成电路封装而被分割。 引线框中的槽有利地允许使用仅制成直线切割的锯片来切割每个引线框。