摘要:
A semiconductor device (20) includes: opposed first (36, 56) and second (34, 54) metal plates; a plurality of semiconductor elements (26, 28, 30, 32, 206, 208, 210, 212, 306, 308, 310, 312) each interposed between the first metal plate (36, 56) and the second metal plate (34, 54); a metal block (44, 50, 314, 316) interposed between the first metal plate (36, 56) and each of the semiconductor elements (26, 28, 30, 32, 206, 208, 210, 212, 306, 308, 310, 312); a solder member (46, 52) interposed between the first metal plate (36, 56) and the metal block (44, 50, 314, 316) and connecting the first metal plate (36, 56) to the metal block (44, 50, 314, 316); and a resin moulding (74) sealing the semiconductor elements (26, 28, 30, 32, 206, 208, 210, 212, 306, 308, 310, 312) and the metal block (44, 50, 314, 316). A face of the first metal plate (36, 56), which is on an opposite side of a face of the first metal plate (36, 56) to which the metal block (44, 50, 314, 316) is connected via the solder member (46, 52), is exposed from the resin moulding (74). The first metal plate (36, 56) has a groove (70, 72) formed along an outer periphery of a region in which the solder member(s) (46, 52) is(are) provided, the groove (70, 72) collectively surrounding the solder member(s) (46, 52) so as to prevent spreading of the solder members (46, 52) on a bonding face of the first metal plate (36, 56). Each of the semiconductor elements (26, 30, 206, 210, 306, 310) may be a power semiconductor switching element, such as an insulated gate bipolar transistor (IGBT), that undergoes switching operation at the time of converting electric power and each of the semiconductor elements (28, 32, 208, 212, 308, 312) may be a reflux diode that is required in order to circulate current at the time of interrupting a corresponding one of the semiconductor elements (26, 30, 206, 210, 306, 310).
摘要:
A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
摘要:
Die Erfindung betrifft ein Verfahren zur Herstellung eines Chipmoduls (90) mit einem Trägersubstrat und zumindest einem auf dem Trägersubstrat angeordneten Chip sowie einer Kontaktleiteranordnung (45) zur Verbindung von Chipanschlussflächen mit auf einer Kontaktseite (56) des Chipmoduls angeordneten Anschlusskontakten (69, 70, 71), bei dem der Chip mit seiner mit den Chipanschlussflächen versehenen Frontseite auf dem Trägersubstrat fixiert wird und nachfolgend die Ausbildung der Kontaktleiteranordnung durch eine Strukturierung einer Kontaktmateriallage des Trägersubstrats erfolgt.
摘要:
The invention relates to a diffusion soldering method in which an electronic component (13) is placed on a substrate (12). The joining surfaces are designed such that cavities (20, 27) are formed in the region of the joining gap (21). The formation of said cavities can be ensured for example by providing depressions in the mounting surface (18) of the component (13) and/or in the contact surface (14) of the substrate (12), the depressions (27) being cup-shaped or advantageously being in the form of channels (20) that surround columnar structural elements (22), the end faces of said structural elements (22) forming the mounting surface (18) or the contact surface (14) for the connection. The cavities (20, 27) are advantageous in that solder material (19) can leak into the cavities when the component (13) is placed on the contact surface (14) of the substrate (12) in order to achieve the required width of the joining gap (21). Thus, the joining gap (21) can be selected so as to have a width so narrow that the joining gap is formed with a diffusion zone (24) which bridges the joining gap (21) upon soldering. In this manner, a diffusion solder connection is produced in an advantageous manner even when using standard solder. The invention further relates to an electronic assembly (11) which has been produced in the aforementioned manner.