公开(公告)号：JP2009152535A

公开(公告)日：2009-07-09

申请号：JP2008198305

申请日：2008-07-31

申请人： Samsung Electro Mech Co Ltd ,  三星電機株式会社

发明人： IKEGUCHI NOBUYUKI ,  SOHN KEUNGJIN ,  SHIN JOON-SIK ,  PARK JUNG-HWAN

IPC分类号： H01L25/065 ,  H01L23/12 ,  H01L25/07 ,  H01L25/18

CPC分类号： H05K1/144 ,  H01L23/13 ,  H01L23/145 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0366 ,  H05K1/056 ,  H05K1/182 ,  H05K3/4608 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674

摘要： PROBLEM TO BE SOLVED: To prevent damage of a semiconductor chip being an electronic element incorporated in a multilayer printed circuit board; to reduce manufacturing cost; to prevent a crack of the board and the electronic element by stress relaxation of a connection member; to prevent a defect such as warpage or torsion; and to prevent reliability degradation by temperature change influencing the reliability of a semiconductor plastic package.
SOLUTION: This method of manufacturing a semiconductor package includes steps of: forming a first board (110); forming second boards (120), in each of which a cavity (160) is formed; attaching the respective second boards (120) to both sides of the first board (110), such that the second boards are electrically connected with the first board 110; and connecting the electronic element to the first board (110) by a flip chip method by incorporating the electronic element in the cavity (160).
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：为了防止作为并入多层印刷电路板中的电子元件的半导体芯片的损坏; 降低制造成本; 以通过连接构件的应力松弛来防止板和电子元件的裂纹; 以防止翘曲或扭曲等缺陷; 并且通过影响半导体塑料封装的可靠性的温度变化来防止可靠性降低。 解决方案：制造半导体封装的该方法包括以下步骤：形成第一板（110）; 形成第二板（120），其中每个板形成有空腔（160）; 将相应的第二板（120）连接到第一板（110）的两侧，使得第二板与第一板110电连接; 以及通过将所述电子元件并入所述空腔（160）中，通过倒装芯片方法将所述电子元件连接到所述第一板（110）。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPWO2007043714A1

公开(公告)日：2009-04-23

申请号：JP2007540236

申请日：2006-10-16

申请人： イビデン株式会社

发明人： 宗太郎 伊藤 ,  宗太郎 伊藤 ,  通昌 高橋 ,  通昌 高橋 ,  幸信 三門 ,  幸信 三門

IPC分类号： H05K3/46 ,  H01L23/12

CPC分类号： H01L24/83 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/096 ,  H05K2201/10477 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2224/13109

摘要： 半導体素子が収容されている樹脂絶縁層上に、他の樹脂絶縁層と導体回路とが順次形成され、前記半導体素子と導体回路との間がビアホールを介して電気的に接続されてなる多層プリント配線板において、樹脂絶縁層に設けた凹部内に半導体素子を収容し、その凹部の底面には半導体素子を載置する金属層を形成してなる多層プリント配線板あるいは半導体素子実装基板である。それにより、内蔵された半導体素子がビアホールを介して電気接続を有する多層プリント配線板が得られる。

公开(公告)号：JP2008251608A

公开(公告)日：2008-10-16

申请号：JP2007087662

申请日：2007-03-29

申请人： Casio Comput Co Ltd ,  カシオ計算機株式会社

发明人： NEGISHI YUJI

IPC分类号： H01L25/00 ,  G01R31/28 ,  H01L21/822 ,  H01L23/12 ,  H01L27/04

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L22/32 ,  H01L23/5385 ,  H01L23/552 ,  H01L25/03 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To realize mounting state inspection and function inspection of course after completion and also even in the course of manufacturing process in the semiconductor device where a semiconductor structure body is mounted face down under a circuit board. SOLUTION: A lower circuit board 11 having an aperture 13 is provided to a peripheral part of a circuit board 1, a semiconductor structure body 31 is provided under the circuit board 1 within an aperture 13 of the lower circuit board 11, and an external connection pads 15a, 15b and test connection pads 15c are provided at the lower surface of the lower circuit board 1. Thereby, mounting state inspection and function inspection can be conducted of course after completion of the device and even in the course of the manufacturing process. COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：为了在半导体结构体安装在电路板的正下方的半导体器件的半导体器件中，即使在制造过程中也实现安装状态检查和功能检查。 解决方案：具有孔13的下电路板11设置在电路板1的周边部分，半导体结构体31设置在电路板1的下面的电路板11的孔13内，以及 外部连接焊盘15a，15b和测试连接焊盘15c设置在下部电路板1的下表面处。因此，可以在装置完成之后进行安装状态检查和功能检查，并且即使在 制造工艺。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP4148201B2

公开(公告)日：2008-09-10

申请号：JP2004234053

申请日：2004-08-11

申请人： ソニー株式会社

发明人： 康春 中村 ,  喜輝 川上

IPC分类号： H05K7/20 ,  H05K1/02 ,  H05K1/14

CPC分类号： H05K1/144 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/467 ,  H01L23/49833 ,  H01L23/5385 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/16195 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/0272 ,  H05K1/186 ,  H05K3/284 ,  H05K3/4614 ,  H05K3/4697 ,  H05K2201/064 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2203/063 ,  H01L2924/00014

摘要： An electronic circuit device includes at least a first substrate and a second substrate, a spacer substrate interposed between the first substrate and the second substrate, an electronic component interposed between the first substrate and the second substrate, and at least one through-hole formed on the second circuit substrate opposing the first circuit substrate. The spacer substrate mutually connects the first substrate and the second substrate. The electronic component is connected to the first circuit substrate with the active surface of the electronic component. The through-hole penetrates from a first surface of the second circuit substrate opposing the first substrate to a second surface of the second circuit substrate. The first circuit substrate is connected to the electronic component.

公开(公告)号：JP2008159694A

公开(公告)日：2008-07-10

申请号：JP2006344690

申请日：2006-12-21

申请人： Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

发明人： HARUHARA MASAHIRO

IPC分类号： H01L23/32

CPC分类号： H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  Y10T428/24802 ,  H01L2224/0401

摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of an electronic component having conductive patterns formed on both the surfaces of a substrate. SOLUTION: The manufacturing method of an electronic component 200 has: a first step of forming a reinforcing portion equipped substrate to be processed having a substrate body to be processed and a reinforcing portion of the substrate body erecting on the first main surface of the substrate to be processed; a second step of forming a first conductive pattern on the first main surface side of the substrate main body to be processed and a second conductive pattern on the second main surface side of the substrate main body to be processed; and a third step of cutting the substrate main body to be processed to remove the reinforcing section and dividing the substrate main body to be processed into discrete pieces. COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：提供一种在基板的两个表面上形成有导电图案的电子部件的制造方法。 电子部件200的制造方法具有如下工序：第一工序，形成加工部件的被加工基板，具有被加工基板主体和基板主体的加强部，该基板主体的第一主面 要加工的基材; 在待加工的基板主体的第一主表面侧上形成第一导电图案的第二步骤和待处理的基板主体的第二主表面侧上的第二导电图案; 以及第三步骤，切割待加工的基板主体以移除加强部分并将要加工的基板主体分成离散件。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP4110992B2

公开(公告)日：2008-07-02

申请号：JP2003031269

申请日：2003-02-07

申请人： セイコーエプソン株式会社

发明人： 浩久 中山 ,  俊宏 沢本 ,  哲理 青▲柳▼

IPC分类号： H01L25/10 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L21/56 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0401

摘要： A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.

公开(公告)号：JP2007243207A

公开(公告)日：2007-09-20

申请号：JP2007105802

申请日：2007-04-13

申请人： Seiko Epson Corp ,  セイコーエプソン株式会社

发明人： HASHIMOTO NOBUAKI

IPC分类号： H01L25/18 ,  H01L23/12 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/36 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC分类号： H05K3/4691 ,  H01L23/5385 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/141 ,  H05K1/189 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/4084 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2203/0195 ,  H01L2224/0401

摘要： PROBLEM TO BE SOLVED: To provide an inexpensive wiring board and its manufacturing method, an electronic component and its manufacturing method, a circuit board, and electronic equipment. SOLUTION: A wiring board includes: a first substrate 10 which has an electronic element mounting area 14 and on which a first wiring pattern 12 is formed; and a second substrate 20 which has an area 26 to which at least a part of the first substrate 10 is attached and an electronic element mounting area 24, and on which formed is a second wiring pattern 22 where the first wiring pattern 12 and the second wiring pattern 22 are electrically connected to each other. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：提供廉价的布线板及其制造方法，电子部件及其制造方法，电路板和电子设备。 解决方案：布线板包括：第一基板10，其具有电子元件安装区域14，并且其上形成有第一布线图案12; 以及第二基板20，其具有安装有第一基板10的至少一部分的区域26和电子元件安装区域24，并且形成有第一布线图案12和第二布线图案22的第二布线图案22 布线图案22彼此电连接。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP3648455B2

公开(公告)日：2005-05-18

申请号：JP2000587594

申请日：1999-12-03

申请人： フォームファクター,インコーポレイテッド

发明人： オンドリセク，ダグラス，エス ,  ペダーセン，デイビッド，ブイ

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/00 ,  G01R31/01 ,  G01R31/28 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/48 ,  H01L23/538 ,  H05K3/32 ,  H05K13/00 ,  H05K13/02 ,  H05K13/04

CPC分类号： H01L24/72 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L2223/54473 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00

公开(公告)号：JP3619254B2

公开(公告)日：2005-02-09

申请号：JP52440596

申请日：1996-02-08

申请人： マイクロン テクノロジー,インク.

发明人： キャセイ，デビッド，エイ． ,  ゴウクナー，デレク ,  ワトキンス，チャールズ

IPC分类号： H01J9/34 ,  H01J9/24 ,  H01J9/26 ,  H01J9/32 ,  H01J9/36 ,  H01L21/60 ,  H01L21/98 ,  H01L23/538 ,  H05K3/32 ,  H05K3/36

CPC分类号： H01L25/50 ,  H01J9/241 ,  H01J9/261 ,  H01J9/32 ,  H01J9/36 ,  H01J2329/8625 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H05K3/328 ,  H05K3/368 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2924/20753 ,  H01L2924/00015 ,  H01L2224/05599

公开(公告)号：JP3568534B2

公开(公告)日：2004-09-22

申请号：JP51310596

申请日：1995-10-17

申请人： 株式会社ルネサステクノロジ ,  株式会社日立超エル・エス・アイ・システムズ

发明人： 岳 新井 ,  雅彦 西馬 ,  元大 諏訪 ,  千代士 鎌田 ,  裕之 高橋

IPC分类号： H01L21/60 ,  H01L23/13 ,  H01L23/433 ,  H01L23/485 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L25/04 ,  H01L25/18

CPC分类号： H01L23/4985 ,  H01L23/13 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device which can reduce the transmission loss of high-frequency signals and in which a semiconductor chip (6) is facedown-bonded to a ground plane TAB tape (4). The TAB tape (4) is such that a first conductive layer (2) and a second conductive layer (3) are respectively formed on the front and rear sides of an insulating layer (1) and a front-side of the second conductive layer (3) is exposed in an opening made in the insulating layer (1) and Au bumps (7a and 7b) are protruded in the openings of the conductive layers (2) and (3). The pad electrode (5) of the semiconductor chip (6) is matched and bonded to the Au bumps (7a and 7b) on the TAB tape (4) without melting the bumps (7a and 7b). This semiconductor device can be used for information communication equipment and a highly advanced system can be constructed when the device is constituted in a multichip module.