公开(公告)号：US20050085012A1

公开(公告)日：2005-04-21

申请号：US10980381

申请日：2004-11-03

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/44

CPC分类号： H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/72 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.

摘要翻译： 电连接具有带有多个触点的第一表面的微电子部件的方法。 该方法包括以下步骤：通过将具有支撑结构的连接部件和由支撑结构的第一表面基本上彼此平行延伸的多个细长柱与微电子部件并置而形成子组件，使得支撑结构覆盖在表面 所述部件的柱子远离所述部件并且将所述柱电连接到所述微电子部件的触头。

公开(公告)号：US06856235B2

公开(公告)日：2005-02-15

申请号：US09950761

申请日：2001-09-12

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： D21F1/06 ,  D21G9/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L25/18 ,  H01C1/14

CPC分类号： H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of making resistors includes providing a sacrificial layer. Conductive material is then formed over a region of the sacrificial layer. Resistive material is then deposited over the first surface of the sacrificial layer such that the resistive material covers the sacrificial layer and the conductive material. A portion of the sacrificial layer is then removed to expose the conductive material. A method of making resistors includes the steps of providing a sacrificial layer, removing at least a portion of the sacrificial layer from regions of the sacrificial layer so as to create a plurality of cavities within the sacrificial layer, plating said cavities with a conductive material, disposing resistive material over the first surface of the sacrificial layer such that resistive material covers the sacrificial layer and said conductive material, and removing at least a portion of said sacrificial layer to expose the conductive material. In another embodiment, a method of making resistors includes the steps of providing a sacrificial layer having a roughened first surface and a second surface, depositing resistive material over the first surface of the sacrificial layer such that the resistive material covers the first surface of the sacrificial layer, and selectively etching the sacrificial layer to form electrodes.

摘要翻译： 制造电阻器的方法包括提供牺牲层。 然后在牺牲层的区域上形成导电材料。 然后将电阻材料沉积在牺牲层的第一表面上，使得电阻材料覆盖牺牲层和导电材料。 然后去除牺牲层的一部分以暴露导电材料。 制造电阻器的方法包括以下步骤：提供牺牲层，从牺牲层的区域去除牺牲层的至少一部分，以在牺牲层内产生多个空腔，用导电材料镀覆所述空腔， 在所述牺牲层的第一表面上设置电阻材料，使得电阻材料覆盖所述牺牲层和所述导电材料，以及去除所述牺牲层的至少一部分以暴露所述导电材料。 在另一个实施例中，制造电阻器的方法包括以下步骤：提供具有粗糙化的第一表面和第二表面的牺牲层，在牺牲层的第一表面上沉积电阻材料，使得电阻材料覆盖牺牲层的第一表面 层，并且选择性地蚀刻牺牲层以形成电极。

公开(公告)号：US06847107B2

公开(公告)日：2005-01-25

申请号：US10219902

申请日：2002-08-15

申请人： Joseph Fjelstad ,  Konstantine Karavakis

发明人： Joseph Fjelstad ,  Konstantine Karavakis

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/02

CPC分类号： H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/498 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85424 ,  H01L2924/00011 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004

摘要： By causing the movement of charge from a toner to a latent image carrier, the amount of charge of the toner is lowered to an amount of charge suitable for facilitating the transfer of toner so as to improve the transfer efficiency. For this, an image forming apparatus includes a latent image carrier and a developing means for forming a negatively chargeable toner layer composed of two stories or less on a toner carrier by a toner layer thickness regulating member. An electrostatic latent image on the latent image carrier is developed with the toner to form a visible image and the visible image is transferred to a transfer medium. Further, the work function (Φopc) of the surface of the latent image carrier is set to be larger than the work function (Φt) of the toner.

摘要翻译： 微电子组件包括具有包括中心区域和围绕中心区域的周边区域的第一表面的微电子元件，微电子元件包括设置在中心区域中的多个触点。 微电子组件还包括覆盖第一表面的周边区域的顺应性层，柔顺层具有面向微电子元件的第一表面的底表面，面向上远离微电子元件的第一表面的顶表面和一个 或更多的边缘表面在顺应层的顶表面和底表面之间延伸。 多个柔性接合带设置在柔性层上方，使得接合带在顶表面上延伸，并且一个或多个边缘表面和接合带将触头电连接到覆盖顺应层的顶表面的导电端子。

公开(公告)号：US06635514B1

公开(公告)日：2003-10-21

申请号：US09644270

申请日：2000-08-23

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： H01L2100

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of making a semiconductor chip assembly includes the steps of providing a semiconductor chip with contacts and a dielectric substrate wiring layer with terminals, forming a plurality of conductive elastomeric posts such that each post connects one terminal to one contact, and after forming the conductive elastomeric posts, injecting compliant material between the semiconductor chip and the dielectric substrate wiring layer to form a compliant layer. Another method of making a semiconductor chip assembly includes providing a semiconductor chip with contacts and a dielectric substrate wiring layer with terminals, dispensing a conductive elastomeric material over each of the contacts or over each of the terminals, juxtaposing the chip and the wiring layer such that conductive elastomeric material connects each contact to one of the terminals, and after the juxtaposing step, injecting a compliant material between the chip and the wiring layer and around the conductive elastomeric material to form a compliant layer, and curing the conductive elastomeric material and the compliant material.

摘要翻译： 制造半导体芯片组件的方法包括以下步骤：为半导体芯片提供触点和具有端子的电介质基底布线层，形成多个导电弹性体柱，使得每个支柱将一个端子连接到一个触点，并且在形成导电 弹性体柱，在半导体芯片和电介质基板布线层之间注入柔性材料以形成柔顺层。 制造半导体芯片组件的另一种方法包括：提供具有触点的半导体芯片和具有端子的介电衬底布线层，在每个触点上方或每个端子上分配导电弹性体材料，并置芯片和布线层，使得 导电弹性体材料将每个触点连接到一个端子，并且在并置步骤之后，在芯片和布线层之间以及导电弹性体材料周围注入柔性材料以形成柔顺层，并且固化导电弹性体材料和柔性层 材料。

公开(公告)号：US06583444B2

公开(公告)日：2003-06-24

申请号：US09025558

申请日：1998-02-18

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： H01L3112

CPC分类号： H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L31/0203 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts and a rear surface and securing the rear surface of the optoelectronic element over the first surface of the sacrificial layer. The one or more contacts are then electrically interconnected with one or more conductive pads on the sacrificial layer and a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the optoelectronic element and the conductive pads. The encapsulant is then cured the sacrificial layer is at least partially removed so as to leave said one or more conductive pads on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining the bottom of the package. The optoelectronic element may include a light sensitive chip such as an ultraviolet-erasable programmable read-only memory (UV EPROM) or a light emitting chip, such as a light emitting diode (LED).

摘要翻译： 制造微电子封装的方法包括提供具有第一表面的牺牲层，并提供具有包括一个或多个触点和后表面的前表面的光电元件，并将光电子元件的后表面固定在牺牲的第一表面上 层。 然后将一个或多个触点与牺牲层上的一个或多个导电焊盘电互连，并且在牺牲层的第一表面上提供可固化和至少部分透明的密封剂，以封装光电子元件和导电焊盘。 密封剂然后被固化，至少部分去除牺牲层，以便将所述一个或多个导电焊盘留在密封剂的底表面上，密封剂的底表面限定封装的底部。 光电元件可以包括光敏芯片，例如可紫外可擦除可编程只读存储器（UV EPROM）或诸如发光二极管（LED）的发光芯片。

公开(公告)号：US06266872B1

公开(公告)日：2001-07-31

申请号：US08987283

申请日：1997-12-09

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： H05K330

CPC分类号： H01L23/4985 ,  H01L21/4846 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

摘要： A method of making a microelectronic assembly includes providing a connection component including a dielectric element with electrically conductive parts, providing a fugitive material in contact with the dielectric element and providing a curable material on the dielectric element after providing the fugitive material and curing the curable material to provide a compliant element so that the fugitive material isolates the electrically conductive parts from the compliant element. The method also includes storing the connection component with the fugitive material and the compliant element. After the storing step, the fugitive material is removed from the connection component and the electrically conductive parts are then connected to a microelectronic element. The step of removing the fugitive material is generally performed less than 24 hours before the electrically conductive parts are connected together and preferably less than one hour before the parts are connected together. The fugitive material may include a liquid soluble material removable by chemical treatment, or a material which may be removed upon exposure to heat, radiation or ultraviolet light.

摘要翻译： 一种制造微电子组件的方法包括提供包括电介质元件的连接部件与导电部件，提供与电介质元件接触的缓冲材料，并在提供缓冲材料并固化可固化材料之后在电介质元件上提供可固化材料 以提供顺应性元件，使得短暂材料将导电部件与顺应元件隔离。 该方法还包括将连接部件与缓冲材料和顺应元件一起存储。 在存储步骤之后，从连接部件移除短暂材料，然后将导电部件连接到微电子元件。 除去短暂物质的步骤通常在导电部件连接在一起之前不到24小时进行，优选在零件连接在一起之前不到1小时。 短暂的材料可以包括通过化学处理可去除的液体可溶性材​​料，或者可以在暴露于热，辐射或紫外线时被除去的材料。

公开(公告)号：US06261863B1

公开(公告)日：2001-07-17

申请号：US09471973

申请日：1999-12-23

申请人： Masud Beroz ,  Thomas H. DiStefano ,  Anthony B. Faraci ,  Joseph Fjelstad ,  Belgacem Haba

发明人： Masud Beroz ,  Thomas H. DiStefano ,  Anthony B. Faraci ,  Joseph Fjelstad ,  Belgacem Haba

IPC分类号： H01L2144

CPC分类号： H05K3/4092 ,  H01L23/49811 ,  H01L23/4985 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions. A method of making a connection component includes removing material from the conductive structures or the support layer or both to form the anchors.

摘要翻译： 用于诸如半导体芯片的微电子器件的连接部件包括支撑层和延伸穿过支撑层的表面的导电结构。 导电结构具有将它们连接到支撑层，以及可释放或未锚定部分的锚固件。 制造连接部件的方法包括从导电结构或支撑层或两者移除材料以形成锚固件。

公开(公告)号：US06211572B1

公开(公告)日：2001-04-03

申请号：US08739303

申请日：1996-10-29

申请人： Joseph Fjelstad ,  Konstantine Karavakis

发明人： Joseph Fjelstad ,  Konstantine Karavakis

IPC分类号： H01L2348

CPC分类号： H01L21/78 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/498 ,  H01L24/05 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools since the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process. The manufacturing process is also amenable to simultaneous assembly of a multiplicity of undiced chips on a wafer or simultaneous assembly of diced chips in a processing boat.

摘要翻译： 具有扇入引线的兼容半导体芯片封装及其制造方法。 封装或“组件”包含连接在半导体芯片的触头和柔性层的顶表面上的相应端子之间的多个粘结带。 柔性层为处理或将组件固定到外部基底时遇到的粘结带提供应力消除。 芯片封装还包含与粘结带的至少一端相邻的电介质层。 在热循环期间，电介质层减轻与组装和衬底材料的热失配相关的机械应力。 可以在不需要任何接合线路工具的情况下制造组件，因为在制造过程中的标准光刻阶段期间，图案化和形成结合带。 制造过程还适于在晶片上同时组装多个未切割的芯片或在处理舟中同时组装切割的芯片。

公开(公告)号：US06001671A

公开(公告)日：1999-12-14

申请号：US634464

申请日：1996-04-18

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： D21F1/06 ,  D21G9/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L25/18

CPC分类号： H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/49 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3011

摘要： A method of manufacturing a semiconductor chip package. A sacrificial layer is used as a base to selectively form an array of conductive pads such that a central region is defined by the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region between the pads so that the contact bearing surface of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to respective pads, typically by wire bonding a wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the sacrificial layer such that the pads, electrical connections and chip are fully encapsulated, as by an overmolding operation. The encapsulant is then cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

摘要翻译： 一种制造半导体芯片封装的方法。 牺牲层用作基底以选择性地形成导电焊盘的阵列，使得中心区域由焊盘限定。 接下来，半导体芯片的背面附着在焊盘之间的中心区域内的牺牲层，使得芯片的接触支承表面背离牺牲层。 芯片触点然后电连接到相应的焊盘，通常通过在其间引线接合线。 然后将可固化的介电液体密封剂沉积在牺牲层上，使得焊盘，电连接和芯片被完全封装，如通过包覆成型操作。 然后将密封剂固化并且牺牲层被完全去除或者被选择性地去除以暴露焊盘的表面以电连接到PWB和芯片的后表面，以形成从芯片到PWB的直接热路径。

公开(公告)号：US5983492A

公开(公告)日：1999-11-16

申请号：US999758

申请日：1997-11-26

申请人： Joseph Fjelstad

发明人： Joseph Fjelstad

IPC分类号： H01L23/32 ,  H01L23/48 ,  H01L23/498 ,  H05K3/40 ,  H01R9/00

CPC分类号： H05K3/4092 ,  H01L23/32 ,  H01L23/49811 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10T29/49117 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149

摘要： A connector for microelectronic elements includes electrically conductive, elongated leads having contact portions underlying a compliant layer. The contact portion of each lead overlies a pedestal portion of the compliant layer. The pedestal portion is at least partially isolated from the remaining portion of the compliant layer by gaps in the compliant layer. The pedestals may thus deflect horizontally, compensating for relative movement between the connector and the microelectronic element. Portions of the leads spanning the gaps may be curved to facilitate deflection. The pedestals may be attached to a substrate having terminals. A terminal end of each lead is then electrically connected to the terminal in the substrate, either through a plated through-hole, or by bending downward and bonding. The pedestals may support a plurality of leads along their length. Alternatively, the pedestals may support only a single respective lead, in which case the pedestal is isolated from neighboring pedestals and may deflect in a plurality of horizontal directions.

摘要翻译： 用于微电子元件的连接器包括导电的细长导线，其具有位于柔顺层下面的接触部分。 每个引线的接触部分覆盖柔性层的基座部分。 通过顺应层中的间隙，基座部分至少部分地与柔性层的剩余部分隔离。 因此，基座可能水平偏转，补偿连接器和微电子元件之间的相对运动。 跨越间隙的引线的一些部分可以是弯曲的以便于偏转。 基座可以附接到具有端子的基板。 然后，每个引线的末端通过电镀通孔或通过向下弯曲和结合而电连接到衬底中的端子。 基座可以沿其长度支撑多个引线。 或者，基座可以仅支撑单个相应的引线，在这种情况下，基座与相邻的基座隔离并且可以在多个水平方向上偏转。