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    Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring
    103.
    发明申请
    Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring 有权
    用绝缘环形环形成导电TSV的半导体器件和方法

    公开(公告)号：US20130087928A1

    公开(公告)日：2013-04-11

    申请号：US13691578

    申请日：2012-11-30

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Nathapong Suthiwongsunthorn

    IPC: H01L23/538 ,  H01L21/48

    CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die.

    Abstract translation: 半导体晶片具有在晶片的有效表面上形成的绝缘层。 在绝缘层上形成导电层。 第一通孔从半导体晶片的背面通过半导体晶片和绝缘层形成到导电层。 导电材料沉积在第一通孔中以形成导电TSV。 可以在第一通孔中沉积绝缘材料，以在导电通孔内形成绝缘芯。 在形成导电TSV之后，通过半导体晶片和绝缘层从导电TSV周围形成第二通孔，从半导体晶片的背表面到导电层。 绝缘材料沉积在第二通孔中以形成绝缘环形环。 导电通孔可以凹入半导体管芯的表面内或延伸到半导体管芯的表面之上。

    Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
    107.
    发明授权
    Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics 有权

    公开(公告)号：US10204879B2

    公开(公告)日：2019-02-12

    申请号：US14861040

    申请日：2015-09-22

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Yaojian Lin ,  Kang Chen

    IPC: H01L27/12 ,  H01L29/786 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

    Abstract: A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure.

    Semiconductor device and method of forming a package in-fan out package
    108.
    发明授权
    Semiconductor device and method of forming a package in-fan out package 有权

    公开(公告)号：US10068862B2

    公开(公告)日：2018-09-04

    申请号：US15082190

    申请日：2016-03-28

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Byung Tai Do ,  Arnel Senosa Trasporto

    IPC: H01L23/48 ,  H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/50 ,  H01L23/00 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

    Abstract: A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die. The first semiconductor package includes a molded laser package.

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