公开(公告)号：US09443783B2

公开(公告)日：2016-09-13

申请号：US13619877

申请日：2012-09-14

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/03 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14144 ,  H01L2224/14154 ,  H01L2224/14164 ,  H01L2224/14181 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

Abstract translation: 提供了一种三维堆叠半导体器件的系统和方法。 在一个实施例中，将两个或更多个半导体管芯附着到载体并封装。 两个或更多个半导体管芯的连接被暴露，并且两个或更多个半导体管芯可以被薄化以在相对侧上形成连接。 然后可以将另外的半导体管芯置于偏移或悬垂位置中。

公开(公告)号：US09391000B2

公开(公告)日：2016-07-12

申请号：US13445734

申请日：2012-04-12

Applicant: Cheng-Chieh Hsieh ,  Jing-Cheng Lin

Inventor： Cheng-Chieh Hsieh ,  Jing-Cheng Lin

IPC: H01L23/473 ,  H01L21/48

CPC classification number: H01L23/473 ,  H01L21/4882 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer.

Abstract translation: 一种方法包括在集成散热器的表面上形成第一氧化物层，并且在翅片的顶表面上形成第二氧化物层，其中散热片是散热片的一部分。 集成散热器通过第一氧化物层与第二氧化物层的结合而结合到散热器。

公开(公告)号：US09219016B2

公开(公告)日：2015-12-22

申请号：US13247659

申请日：2011-09-28

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H05K7/00 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L22/32 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/13578 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers.

Abstract translation: 工件包括具有顶表面和侧壁的第一含铜柱，以及第一含铜柱的侧壁而不是顶表面上的第一保护层。 测试垫包括具有顶表面和侧壁的第二含铜柱。 测试垫电耦合到第一含铜柱。 第二保护层设置在第二含铜柱的侧壁上，而不是在顶表面上。 第一和第二保护层包括铜和聚合物的化合物，并且是电介质层。

公开(公告)号：US09159687B2

公开(公告)日：2015-10-13

申请号：US13572302

申请日：2012-08-10

Applicant: Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract translation: 用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

公开(公告)号：US08975183B2

公开(公告)日：2015-03-10

申请号：US13370477

申请日：2012-02-10

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L21/44

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards.

Abstract translation: 一种形成半导体结构的方法。 提供了包括安装在其上的多个管芯的半导体基板。 衬底包括靠近模具的第一部分和远离模具的第二部分。 在一些实施例中，第一部分可以包括前侧金属化。 衬底的第二部分变薄，并且在变薄操作之后，在衬底的第二部分中形成多个导电贯通衬底通孔（TSV）。 在变薄之前，第二部分可以不包含金属化。 在一个实施例中，衬底可以是硅插入器。 可以形成另外的背侧金属化以将TSV电连接到其他封装基板或印刷电路板。

公开(公告)号：US08922004B2

公开(公告)日：2014-12-30

申请号：US12846260

申请日：2010-07-29

Applicant: Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US08866301B2

公开(公告)日：2014-10-21

申请号：US12781960

申请日：2010-05-18

Applicant: Yung-Chi Lin ,  Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Yung-Chi Lin ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/29 ,  H01L21/48

CPC classification number: H01L21/4857 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

Abstract translation: 封装系统包括设置在插入器上的第一集成电路。 所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。 第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。 第一集成电路与第一互连结构电耦合。

公开(公告)号：US08698308B2

公开(公告)日：2014-04-15

申请号：US13362913

申请日：2012-01-31

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L29/40

CPC classification number: H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a α ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

Abstract translation: 用于形成凸块结构的机构能够在芯片和基板之间形成凸块结构，消除或降低焊料短路，焊剂残留物和底部填充物中的空隙的风险。 可以通过将粘合凸块结构中的铜柱的总高度除以接合的凸块结构的间隙来限定的α比来限定下限，以避免短路。 也可以建立一个下限以排除芯片封装以避免焊剂残留和底部填充空隙形成。 此外，由于制造工艺限制，铜柱凸起的纵横比具有下限以避免不足的间隙和更高的极限。 通过遵循适当的凸块设计和工艺指南，芯片封装的产量和可靠性可能会增加。

公开(公告)号：US08653658B2

公开(公告)日：2014-02-18

申请号：US13308162

申请日：2011-11-30

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/498 ,  H01L21/50 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.

Abstract translation: 用于形成凸块结构的机构减少了芯片和封装衬底之间的间隙的变化。 通过在电镀后对芯片和/或基板上的凸块结构上的焊料层进行平坦化，可以控制凸块结构的高度，以最小化晶片内部以及晶片位置，图案密度，晶粒尺寸和工艺变化中的变化。 结果，芯片和基板之间的间隔被控制得更均匀。 因此，底部填充质量得到改善。

公开(公告)号：US08643148B2

公开(公告)日：2014-02-04

申请号：US13397204

申请日：2012-02-15

Applicant: Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

Inventor： Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

IPC: H01L21/78

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Abstract translation: 包装部件包括基板，其中基板具有前表面和在前表面上的后表面。 通孔穿过基底。 导电特征设置在衬底的背表面上并电连接到通孔。 第一电介质图案形成导电特征的环覆盖边缘部分。 底部金属（UBM）被布置在导电特征的中心部分上并与其接触。 聚合物接触衬底的侧壁。 将第二电介质图案设置在聚合物上并对准聚合物。 第一和第二电介质图案由相同的电介质材料形成，并且设置在基本上相同的水平。